公开(公告)号：US20170310236A1

公开(公告)日：2017-10-26

申请号：US15646582

申请日：2017-07-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shunichi KAERIYAMA ,  Kouichi YAMAGUCHI ,  Koichi NOSE

IPC: H02M7/06 ,  H04L25/49 ,  H04B3/50 ,  H04L25/02 ,  H04B5/00

CPC classification number: H04B5/0031 ,  H01L2224/451 ,  H01L2224/48137 ,  H01L2924/12032 ,  H01L2924/13091 ,  H04B3/50 ,  H04L25/0266 ,  H04L25/4902 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Provided is a receiving circuit that operates in a power supply system different from a transmitting circuit outputting a transmission signal and receives the transmission signal through an AC coupling device where a primary coil through which the transmission signal flows and a secondary coil having a center tap to which a specified voltage is supplied from an external terminal are magnetically coupled, which includes a pulse width amplifier circuit that holds pulse signals appearing at both ends of the secondary coil for a specified period of time and outputs them as hold signals, respectively, and a differential amplifier that compares a voltage of the hold signal and a voltage of the hold signal and outputs a comparison result.

公开(公告)号：US20130308355A1

公开(公告)日：2013-11-21

申请号：US13865339

申请日：2013-04-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shunichi KAERIYAMA

IPC: H02M7/537

CPC classification number: H02M7/537 ,  H01L2224/48091 ,  H01L2224/48137 ,  H02M5/297 ,  H01L2924/00014

Abstract: The number of ICs used for a power converter is reduced. The power converter includes n power transistors each having an emitter terminal or a source terminal connected to a common line, and driver ICs. Each of the driver ICs includes n pre-drivers that drive the respective n power transistors, and a receiver circuit that is integrated monolithically with the n pre-drivers. The receiver circuit is coupled with a transmitter circuit by AC coupling, and outputs a control signal that controls the n pre-drivers in response to a signal received from the transmitter circuit.

Abstract translation: 用于功率转换器的IC的数量减少。 功率转换器包括n个功率晶体管，每个功率晶体管具有连接到公共线的发射极端子或源极端子以及驱动器IC。 每个驱动器IC包括驱动相应的n个功率晶体管的n个预驱动器，以及与n个前驱动器整体集成的接收器电路。 接收器电路通过AC耦合与发射机电路耦合，并且响应于从发射机电路接收的信号输出控制n个预驱动器的控制信号。

公开(公告)号：US20130287141A1

公开(公告)日：2013-10-31

申请号：US13860040

申请日：2013-04-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shunichi KAERIYAMA

IPC: H04L1/00

CPC classification number: H04L1/0041 ,  H01L2224/48137 ,  H01L2924/1305 ,  H01L2924/13055 ,  H04L1/0023 ,  H04L25/02 ,  H01L2924/00

Abstract: In a semiconductor device, a transmitting circuit generates a delayed data signal and a first delayed retransmission request signal by delaying a data signal and a first retransmission request signal, respectively, and outputs a pulse signal at an edge of the delayed data signal and the first delayed retransmission request signal and prohibits output of the pulse signal at an edge of the first delayed retransmission request signal during a specified period across an edge of the delayed data signal.

公开(公告)号：US20130259144A1

公开(公告)日：2013-10-03

申请号：US13784262

申请日：2013-03-04

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koichi TAKEDA ,  Shunichi KAERIYAMA

IPC: H04L25/02

CPC classification number: H04L25/026 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/30107 ,  H04L25/0266 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A receiver includes a positive pulse determination circuit and a negative pulse determination circuit. The positive pulse determination circuit outputs a first L-level between when a pulse signal having a negative amplitude is detected and when neither a pulse signal having a positive amplitude nor a pulse signal having a negative amplitude is detected; otherwise a first H-level if a pulse signal having a positive amplitude is detected during another period. The negative pulse determination circuit outputs a second L-level between when a pulse signal having a positive amplitude is detected and when neither a pulse signal having a positive amplitude nor a pulse signal having a negative amplitude is detected; otherwise a second H-level is output if a pulse signal having a negative amplitude is detected during the other period.

Abstract translation: 接收机包括正脉冲确定电路和负脉冲确定电路。 正脉冲确定电路在检测到具有负幅度的脉冲信号之间并且既没有检测到具有正振幅的脉冲信号也没有检测到具有负幅度的脉冲信号时，输出第一L电平; 否则如果在另一周期期间检测到具有正振幅的脉冲信号，则第一H电平。 负脉冲判定电路在检测到具有正振幅的脉冲信号之间并且既没有检测到具有正振幅的脉冲信号也没有检测到具有负幅度的脉冲信号时，输出第二L电平; 否则如果在其他周期内检测到具有负幅度的脉冲信号，则输出第二H电平。

公开(公告)号：US20180269773A1

公开(公告)日：2018-09-20

申请号：US15856692

申请日：2017-12-28

Applicant: Renesas Electronics Corporation

Inventor： Shunichi KAERIYAMA

IPC: H02M1/08 ,  H02M5/458 ,  H02M1/42 ,  H02M7/5395

CPC classification number: H02M1/08 ,  H02M1/4208 ,  H02M5/458 ,  H02M7/53873 ,  H02M7/5395 ,  H02M2001/0009 ,  H02M2001/008 ,  H02P27/08

Abstract: An object of the invention is to improve precision of current detection in a switching system having plural switching circuits. A first PWM timing generation circuit generates an edge timing of a PWM signal by using a comparison value and a count value and drives a first switching circuit. A second PWM timing generation circuit generates an edge timing of a PWM signal of plural phases by using a comparison value and a count value and drives a second switching circuit. One of the switching circuits is an inverter circuit of a common shunt type in which a shunt resistor is provided commonly for plural phases. One of the PWM timing generation circuits shifts the generated edge timing so that an interval between an edge timing of one of the circuits and an AD conversion timing of the other becomes equal to or larger than a predetermined reference value.

公开(公告)号：US20170237363A1

公开(公告)日：2017-08-17

申请号：US15585204

申请日：2017-05-03

Applicant: Renesas Electronics Corporation

Inventor： Shunichi KAERIYAMA

IPC: H02M7/5387 ,  H02M1/084

CPC classification number: H02M7/5387 ,  G01R19/0092 ,  H02M1/084 ,  H02M2001/0009 ,  H03K17/687

Abstract: A power control circuit according to one embodiment includes an H-bridge circuit formed using a plurality of power transistors. The power transistors are respectively connected to current measurement circuits that measure currents flowing through the power transistors. Each of the power transistors includes a main emitter and a sense emitter through which a current corresponding to a current flowing through the main emitter flows. Each of the current measurement circuits measures a current flowing through each of the power transistors by using a current flowing through the sense emitter included in the power transistor. A control circuit controls the power transistors based on current values respectively measured by the current measurement circuits.

公开(公告)号：US20160079139A1

公开(公告)日：2016-03-17

申请号：US14941973

申请日：2015-11-16

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shunichi KAERIYAMA

IPC: H01L23/34 ,  H01L27/02 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L23/34 ,  H01L23/345 ,  H01L23/5222 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/62 ,  H01L23/645 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L25/16 ,  H01L27/0248 ,  H01L2224/05554 ,  H01L2224/48137 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A semiconductor device includes an AC coupling element, and a temperature monitoring unit that outputs a temperature monitor signal, the temperature monitoring unit has a first temperature monitoring element that outputs the temperature monitor signal, and the first temperature monitoring element is arranged in a region immediately below or a region adjacent to the AC coupling element.

Abstract translation: 半导体装置包括AC耦合元件和输出温度监视信号的温度监视单元，所述温度监视单元具有输出温度监视信号的第一温度监视元件，并且第一温度监视元件被立即布置在区域中 或与AC耦合元件相邻的区域。

公开(公告)号：US20150084209A1

公开(公告)日：2015-03-26

申请号：US14487762

申请日：2014-09-16

Applicant: Renesas Electronics Corporation

Inventor： Shinichi UCHIDA ,  Kenji NISHIKAWA ,  Masato KANNO ,  Mika YONEZAWA ,  Shunichi KAERIYAMA ,  Toshinori KIYOHARA

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/495

CPC classification number: H01L23/49575 ,  H01L23/3107 ,  H01L23/3171 ,  H01L23/48 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49551 ,  H01L23/5227 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L28/10 ,  H01L29/0657 ,  H01L2224/05554 ,  H01L2224/06155 ,  H01L2224/06181 ,  H01L2224/27003 ,  H01L2224/27334 ,  H01L2224/29034 ,  H01L2224/29139 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/32057 ,  H01L2224/32135 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48249 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/743 ,  H01L2224/75745 ,  H01L2224/83141 ,  H01L2224/83191 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a chip mounting part, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip is mounted over the chip mounting part in a direction in which its first principal plane faces the chip mounting part. A part of the second semiconductor chip is mounted over the chip mounting part in a direction in which its third principal plane faces the first semiconductor chip. The element mounting part has a notch part. A part of the second semiconductor chip overlaps the notch part. In a region of the third principal plane of the second semiconductor chip that overlaps the notch part, a second electrode pad is provided.

Abstract translation: 半导体器件具有芯片安装部分，第一半导体芯片和第二半导体芯片。 第一半导体芯片沿其第一主平面面向芯片安装部分的方向安装在芯片安装部分上。 第二半导体芯片的一部分在其第三主平面面向第一半导体芯片的方向上安装在芯片安装部分上。 元件安装部分具有凹口部分。 第二半导体芯片的一部分与切口部分重叠。 在与切口部重叠的第二半导体芯片的第三主平面的区域中，设置有第二电极焊盘。

公开(公告)号：US20230170898A1

公开(公告)日：2023-06-01

申请号：US17965335

申请日：2022-10-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shunichi KAERIYAMA

IPC: H03K17/687 ,  H03K7/08 ,  H02M1/08 ,  H02M1/38

CPC classification number: H03K17/6871 ,  H03K7/08 ,  H02M1/08 ,  H02M1/38 ,  H03K2217/0063 ,  H03K2217/0072 ,  H03K2217/0081 ,  H02P27/08

Abstract: A semiconductor device includes a galvanic isolator; a transmitting circuit that transmits a transmission signal via the galvanic isolator; a receiving circuit that receives a received signal corresponding to the transmission signal via the galvanic isolator; an encoding circuit that encodes two input signals and generates the transmission signal; and a decoding circuit that decodes the two input signals from the received signals.

公开(公告)号：US20200343715A1

公开(公告)日：2020-10-29

申请号：US16841224

申请日：2020-04-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shunichi KAERIYAMA

IPC: H02H7/12 ,  G01R31/26 ,  H02H1/00

Abstract: A drive device comprises a sensor for detecting a state of stress applied to a power transistor, a threshold voltage setting circuit for outputting a threshold voltage, an anomaly monitor circuit for determining whether or not a state of stress is abnormal by comparing a detected voltage of the sensor with the threshold voltage, and a control circuit for fixing the power transistor to either on or off when the state of stress is determined to be abnormal by the anomaly monitor circuit. When an operating mode is a test mode, the control circuit tests whether the anomaly monitor circuit determines the state of the stress is abnormal or not by switching a level of the threshold voltage set by the threshold voltage setting circuit so as to determine that a state of the stress applied to the power transistor is abnormal in the normally operating anomaly monitor circuit.