公开(公告)号：US20130127068A1

公开(公告)日：2013-05-23

申请号：US13745118

申请日：2013-01-18

Applicant: Renesas Electronics Corporation

Inventor： Yoshihisa MATSUBARA

IPC: H01L23/535

CPC classification number: H01L23/535 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a first interconnection including a first end, a second interconnection connected to the first interconnection and including a width being gradually wider towards the first end, a third interconnection and a fourth interconnection, the third interconnection and the fourth interconnection being arranged to sandwich the second interconnection. The first interconnection, the second interconnection, the third interconnection, and the fourth interconnection are each formed in a same layer and a width of the first interconnection is wider than a width of the second interconnection.

Abstract translation: 一种半导体器件包括第一互连，其包括第一端，连接到第一互连的第二互连，并且包括朝向第一端逐渐变宽的宽度，第三互连和第四互连，第三互连和第四互连被布置为 夹心第二个互连。 第一互连，第二互连，第三互连和第四互连各自形成在相同的层中，并且第一互连的宽度比第二互连的宽度宽。

公开(公告)号：US20180301462A1

公开(公告)日：2018-10-18

申请号：US15900664

申请日：2018-02-20

Applicant: Renesas Electronics Corporation

Inventor： Yoshihisa MATSUBARA

IPC: H01L27/11546 ,  H01L29/788 ,  H01L29/423 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L27/11546 ,  H01L21/26513 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/42344 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/7883 ,  H01L29/792

Abstract: In a semiconductor device including a higher-breakdown-voltage MISFET, an improvement is achieved in the breakdown voltage of the MISFET, while preventing an increase in the area of the MISFET. A gate pattern including a gate electrode of the higher-breakdown-voltage MISFET is formed higher in level than a gate pattern including a gate electrode of a lower-breakdown-voltage MISFET. An n+-type semiconductor region included in each of source/drain regions of the higher-breakdown-voltage MISFET is formed deeper than an n+-type semiconductor region included in each of source/drain regions of the lower-breakdown-voltage MISFET.

公开(公告)号：US20180061735A1

公开(公告)日：2018-03-01

申请号：US15798971

申请日：2017-10-31

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshihisa MATSUBARA

IPC: H01L23/373 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31

CPC classification number: H01L23/3733 ,  H01L21/565 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/373 ,  H01L23/4334 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/04042 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29393 ,  H01L2224/29499 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45686 ,  H01L2224/45687 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/83855 ,  H01L2224/85 ,  H01L2224/92125 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/32245 ,  H01L2924/00

Abstract: Performance of a semiconductor device is improved. Graphene particles are mixedly added in a sealing resin covering a semiconductor chip. The graphene particles are thus mixedly added in the sealing resin, thereby thermal conduction of the sealing resin is improved, and thus radiation performance of the semiconductor device can be improved. Graphene is a sheet of sp2 bonded carbon atoms having a monolayer thickness. Graphene has a structure where hexagonal lattices, each of which is formed of carbon atoms and bonds of the carbon atoms, are planarly spread. Graphene is preferably used as heat transfer filler because of its high thermal conductivity and light weight.

公开(公告)号：US20180090451A1

公开(公告)日：2018-03-29

申请号：US15655831

申请日：2017-07-20

Applicant: Renesas Electronics Corporation

Inventor： Yoshihisa MATSUBARA ,  Yasuhiro SHIMADA ,  Yoshitaka KYOUGOKU

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/49877 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/13023 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2924/16235 ,  H01L2924/16251

Abstract: While strength of a wiring board in a semiconductor substrate is ensured, thermal conductivity is increased. A BGA includes a wiring board having an upper surface and a lower surface, a semiconductor chip mounted on the upper surface of the wiring board, and ball electrodes that are a plurality of external terminals provided on the lower surface of the wiring board. The wiring board includes an insulation layer arranged between wiring layers. The insulation layer includes a resin layer, another resin layer, and an electrically conducting layer arranged between the resin layer and the other resin layer. The electrically conducting layer is formed by a lamination of a graphite sheet and a metal layer.

公开(公告)号：US20170358517A1

公开(公告)日：2017-12-14

申请号：US15480700

申请日：2017-04-06

Applicant: Renesas Electronics Corporation

Inventor： Yoshihisa MATSUBARA

IPC: H01L23/373 ,  H01L23/31 ,  H01L21/48 ,  H01L23/367 ,  H01L23/00

CPC classification number: H01L23/3738 ,  H01L21/4871 ,  H01L21/4882 ,  H01L23/3128 ,  H01L23/3164 ,  H01L23/3185 ,  H01L23/3672 ,  H01L23/373 ,  H01L24/16 ,  H01L2224/16157

Abstract: A semiconductor device including a semiconductor chip and a heat dissipation unit (heat sink) is configured as follows. The heat dissipation unit (heat sink) includes a resin tape, and a fin constituted of a graphite sheet and protruding from the resin tape. The fin, including graphene, is disposed on the semiconductor chip such that the graphene is disposed in a direction crossing a surface of the semiconductor chip. The heat dissipation unit is a rolled body in which the graphite sheet and the resin tape are layered and rolled. Thus, by use of the graphene as a constituent material of the fin, thermal conductivity is improved, whereby a heat dissipation characteristic is improved. Furthermore, since the fin is protruded from the resin tape, an exposed area of the fin is increased, and accordingly, the heat dissipation characteristic can be improved.

公开(公告)号：US20170170095A1

公开(公告)日：2017-06-15

申请号：US15374478

申请日：2016-12-09

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshihisa MATSUBARA

IPC: H01L23/373 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31

CPC classification number: H01L23/3733 ,  H01L21/565 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/373 ,  H01L23/4334 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/04042 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29393 ,  H01L2224/29499 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45686 ,  H01L2224/45687 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/83855 ,  H01L2224/85 ,  H01L2224/92125 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/32245 ,  H01L2924/00

Abstract: Performance of a semiconductor device is improved. Graphene particles are mixedly added in a sealing resin covering a semiconductor chip. The graphene particles are thus mixedly added in the sealing resin, thereby thermal conduction of the sealing resin is improved, and thus radiation performance of the semiconductor device can be improved. Graphene is a sheet of sp2 bonded carbon atoms having a monolayer thickness. Graphene has a structure where hexagonal lattices, each of which is formed of carbon atoms and bonds of the carbon atoms, are planarly spread. Graphene is preferably used as heat transfer filler because of its high thermal conductivity and light weight.

公开(公告)号：US20160218060A1

公开(公告)日：2016-07-28

申请号：US14994263

申请日：2016-01-13

Applicant: Renesas Electronics Corporation

Inventor： Yoshihisa MATSUBARA ,  Takashi ISHIGAMI

IPC: H01L23/528 ,  H01L23/532 ,  H01L29/49 ,  H01L27/088 ,  H01L29/66

Abstract: An improvement is achieved in the performance of a semiconductor-device. The semiconductor device includes MISFETs formed in the upper surface of a substrate, a plurality of wiring layers stacked over the upper surface of the substrate, and a plurality of plugs each coupling two of the wiring layers to each other. The wiring layers located under the uppermost wiring layer include wires. The uppermost wiring layer includes a pad, an insulating film formed over the pad, and an opening extending through the insulating film and reaching the pad. The MISFETs and the wires overlap the opening in plan view. None of the plurality of plugs overlaps the opening in plan view.

Abstract translation: 半导体器件的性能得到改善。 半导体器件包括形成在衬底的上表面中的MISFET，在衬底的上表面上堆叠的多个布线层，以及将两个布线层彼此耦合的多个插塞。 位于最上层布线层下方的布线层包括导线。 最上面的布线层包括衬垫，形成在衬垫上的绝缘膜，以及延伸穿过绝缘膜并到达衬垫的开口。 MISFET和电线在平面图中与开口重叠。 多个插头中的任一个在平面图中与开口重叠。

公开(公告)号：US20140057432A1

公开(公告)日：2014-02-27

申请号：US14067472

申请日：2013-10-30

Applicant: Renesas Electronics Corporation

Inventor： Yoshihisa MATSUBARA

IPC: H01L21/768

CPC classification number: H01L23/528 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for manufacturing a semiconductor device includes forming a first interconnect over the semiconductor substrate; forming an interlayer dielectric film over the first interconnect; forming a hole in the interlayer dielectric film such that the hole reaches the first interconnect; forming a trench in the interlayer dielectric film; and embedded a conductive film in the hole and the trench, thereby a via is formed in the hole and a second interconnect in the trench, wherein, in a planar view, the first interconnect extends in a first direction, wherein, in a planar view, the second interconnect extends in a second direction which is perpendicular to the first direction, and wherein a maximum width of the via in the second direction is larger than a maximum width of the via in the first direction.

Abstract translation: 一种制造半导体器件的方法包括：在所述半导体衬底上形成第一互连; 在所述第一互连上形成层间绝缘膜; 在所述层间电介质膜中形成孔，使得所述孔到达所述第一互连; 在层间绝缘膜中形成沟槽; 并且在所述孔和所述沟槽中嵌入导电膜，从而在所述孔中形成通孔，在所述沟槽中形成第二互连件，其中，在平面图中，所述第一互连件沿第一方向延伸，其中，在平面图中 所述第二互连件在垂直于所述第一方向的第二方向上延伸，并且其中所述通孔在所述第二方向上的最大宽度大于所述通孔在所述第一方向上的最大宽度。