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44 条记录 (耗时 0.022 秒)

    Edge termination in MOS transistors
    2.
    发明申请
    Edge termination in MOS transistors 失效

    公开(公告)号：US20050156232A1

    公开(公告)日：2005-07-21

    申请号：US11066408

    申请日：2005-02-25

    申请人： Raymond Hueting ,  Erwin Hijzen ,  Michael In't Zandt

    发明人： Raymond Hueting ,  Erwin Hijzen ,  Michael In't Zandt

    IPC分类号： H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78 ,  H01L29/76 ,  H01L21/336

    CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/7397 ,  H01L29/7811

    摘要： A RESURF trench gate MOSFET has a sufficiently small pitch (close spacing of neighbouring trenches) that intermediate areas of the drain drift region are depleted in the blocking condition of the MOSFET. However, premature breakdown can still occur in this known device structure at the perimeter/edge of the active device area and/or adjacent the gate bondpad. To counter premature breakdown, the invention adopts two principles: the gate bondpad is either connected to an underlying stripe trench network surrounded by active cells, or is directly on top of the active cells, and a compatible 2D edge termination scheme is provided around the RESURF active device area. These principles can be implemented in various cellular layouts e.g. a concentric annular device geometry, which may be circular or rectangular or ellipsoidal, in the active area and in the edge termination, or a device array of such concentric hexagonal or circular stripe cells, or a device array of square active cells with stripe edge cells, or a device array of hexagonal active cells with an edge termination of hexagonal edge cells.

    Insulated gate power semiconductor devices
    5.
    发明申请
    Insulated gate power semiconductor devices 失效
    绝缘栅功率半导体器件

    公开(公告)号：US20060189063A1

    公开(公告)日：2006-08-24

    申请号：US10564214

    申请日：2003-07-12

    申请人： Raymond Hueting ,  Erwin Hijzen ,  Michael In't Zandt

    发明人： Raymond Hueting ,  Erwin Hijzen ,  Michael In't Zandt

    IPC分类号： H01L21/8238 ,  H01L29/76

    CPC分类号： H01L29/7813 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238

    摘要： A trench-gate semiconductor device (100) has a trench network (STR1), ITR1) surrounding a plurality of closed transistor cells (TCS). The trench network comprises segment trench regions (STR1) adjacent sides of the transistor cells (TCS) and intersection trench regions (ITR1) adjacent corners of the transistor cells. As shown in FIG. 16 which is a section view along the line II-II of FIG. 11, the intersection trench regions (ITR1) each include insulating material (21D) which extends from the bottom of the intersection trench region with a thickness which is greater than the thickness of the insulating material (21B1) at the bottom of the segment trench regions (STR1). The greater thickness of the insulating material (21D) extending from the bottom of the intersection trench regions (ITR1) is effective to increase the drain-source reverse breakdown voltage of the device (100). The insulating material (21D) which extends from the bottom of each intersection trench region (ITR1) may extend upwards to thicken the insulating material at the corners of the cells (TCS) over at least part of the vertical extent of the channel-accommodating body region (23) so as to increase the threshold voltage of the device.

    摘要翻译： 沟槽栅极半导体器件（100）具有围绕多个闭合晶体管单元（TCS）的沟槽网络（STR1），ITR 1）。 沟槽网络包括晶体管单元（TCS）的相邻侧的分段沟槽区域（STR 1）和晶体管单元的相邻角的交叉沟槽区域（ITR 1）。 如图所示。 图16是沿图1的II-II线的剖视图。 如图11所示，交点沟槽区域（ITR 1）各自包括从交叉沟槽区域的底部延伸的绝缘材料（21D），其厚度大于绝缘材料（21B 1）的底部的厚度 段沟槽区域（STR 1）。 从交叉沟槽区域（ITR 1）的底部延伸的绝缘材料（21D）的较大厚度对于增加器件（100）的漏 - 源反向击穿电压是有效的。 从每个交叉沟槽区域（ITR 1）的底部延伸的绝缘材料（21D）可以向上延伸，以在通道的垂直方向的至少一部分的至少部分的细胞（TCS）上增厚绝缘材料， 容纳体区域（23），以增加装置的阈值电压。

    Trench mosfet
    6.
    发明申请
    Trench mosfet 有权
    沟渠mosfet

    公开(公告)号：US20070108515A1

    公开(公告)日：2007-05-17

    申请号：US10580619

    申请日：2004-11-26

    申请人： Raymond Hueting ,  Erwin Hijzen

    发明人： Raymond Hueting ,  Erwin Hijzen

    IPC分类号： H01L29/94

    CPC分类号： H01L29/7813 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/4238

    摘要： The invention relates to a trench MOSFET with drain (8), dπ ft region (10) body (12) and source (14). In order to improve the figure of meπt for use of the MOSFET as control and sync FETs, the trench (20) is partially filled with dielectric (24) adjacent to the drift region (10) and a graded doping profile is used in the dπft region (10)

    摘要翻译： 本发明涉及一种具有漏极（8），dpi ft（10）主体（12）和源极（14）的沟槽MOSFET。 为了改善使用MOSFET作为控制和同步FET的mepit图，沟槽（20）部分地被与漂移区（10）相邻的电介质（24）填充，并且在dpift中使用渐变掺杂分布 地区（10）

    Semiconductor device and method of manufacture thereof
    9.
    发明授权
    Semiconductor device and method of manufacture thereof 有权
    半导体装置及其制造方法

    公开(公告)号：US08476675B2

    公开(公告)日：2013-07-02

    申请号：US12918524

    申请日：2009-02-26

    申请人： Philippe Meunier-Beillard ,  Johannes J. T. M. Donkers ,  Erwin Hijzen

    发明人： Philippe Meunier-Beillard ,  Johannes J. T. M. Donkers ,  Erwin Hijzen

    IPC分类号： H01L29/66

    CPC分类号： H01L21/8249 ,  H01L27/0623 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/165 ,  H01L29/42304 ,  H01L29/456 ,  H01L29/66242 ,  H01L29/7378

    摘要： A semiconductor device (10) comprising a bipolar transistor and a field 5 effect transistor within a semiconductor body (1) comprising a projecting mesa (5) within which are at least a portion of a collector region (22c and 22d) and a base region (33c) of the bipolar transistor. The bipolar transistor is provided with an insulating cavity (92b) provided in the collector region (22c and 22d). The insulating cavity (92b) may be provided by providing a layer (33a) in the collector region (22c), creating an access path, for example by selectively etching polysilicon towards monocrystalline, and removing a portion of the layer (33a) to provide the cavity using the access path. The layer (33a) provided in the collector region may be of SiGe:C. By blocking diffusion from the base region the insulating cavity (92b) provides a reduction in the base collector capacitance and can be described as defining the base contact.

    摘要翻译： 一种半导体器件（10），包括在半导体本体（1）内的双极晶体管和场效应晶体管，包括突出的台面（5），其中集电极区域（22c和22d）的至少一部分和基极区域 （33c）。 双极晶体管设置有设置在集电区域（22c和22d）中的绝缘腔（92b）。 可以通过在集电极区域（22c）中设置层（33a）来提供绝缘腔（92b），从而产生存取路径，例如通过选择性地将多晶硅蚀刻成单晶，并去除层（33a）的一部分以提供 使用进入路径的空腔。 设置在集电区域中的层（33a）可以是SiGe：C。 通过阻挡从基极区域的扩散，绝缘腔（92b）提供基极集电极电容的减小，并且可以被描述为限定基极接触。