公开(公告)号：US11923340B2

公开(公告)日：2024-03-05

申请号：US17405130

申请日：2021-08-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeongkwon Ko ,  Jinwoo Park ,  Jaekyung Yoo ,  Teakhoon Lee

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L23/295 ,  H01L23/3135 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/50 ,  H01L24/05 ,  H01L24/06 ,  H01L24/17 ,  H01L24/33 ,  H01L24/73 ,  H01L24/92 ,  H01L25/18 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/17181 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92143 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06586

Abstract: A semiconductor package includes a package substrate on which a base chip is disposed. A first semiconductor chip is disposed on the base chip. A second semiconductor chip is disposed on the first semiconductor chip. An inner mold layer surrounds an upper surface of the base chip and respective side surfaces of the first semiconductor chip and the second semiconductor chip. A first outer mold layer is interposed between the package substrate and the base chip while covering at least a portion of a side surface of the base chip. A second outer mold layer is disposed on the first outer mold layer while covering at least a portion of a side surface of the inner mold layer. The second outer mold layer is spaced apart from the package substrate. The first outer mold layer and the second outer mold layer have different viscosities.

公开(公告)号：US11791282B2

公开(公告)日：2023-10-17

申请号：US17083932

申请日：2020-10-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaekyung Yoo ,  Yeongkwon Ko ,  Jayeon Lee ,  Jaeeun Lee ,  Teakhoon Lee

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/528 ,  H01L23/532 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49833 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50

Abstract: A semiconductor package comprises a substrate; an interposer on the substrate; a first underfill between the substrate and the interposer; at least one logic chip and at least one memory stack on the interposer; and a molding material on the interposer while surrounding a side surface of the at least one logic chip and a side surface of the at least one memory stack. The molding material includes areas having different heights. The first underfill covers a portion of the molding material.

公开(公告)号：US20250149494A1

公开(公告)日：2025-05-08

申请号：US18940264

申请日：2024-11-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaekyung Yoo ,  Jinwoo Park ,  Kyonghwan Koh ,  Woohyeong Kim ,  Taeryong Kim

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/29 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18 ,  H10B80/00

Abstract: A semiconductor package includes a first substrate, a first semiconductor chip on an upper surface of the first substrate, a first bump between the first substrate and the first semiconductor chip, a first underfill layer that fills a center portion of a space between the first substrate and the first semiconductor chip, and a first molding member that covers an upper surface and side surfaces of the first semiconductor chip, and fills a periphery portion of the space between the first substrate and the first semiconductor chip, wherein a volume occupied by the first molding member in the space between the first substrate and the first semiconductor chip is greater than a volume occupied by the first underfill layer in the space between the first substrate and the first semiconductor chip.

公开(公告)号：US12062639B2

公开(公告)日：2024-08-13

申请号：US17529798

申请日：2021-11-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaekyung Yoo ,  Jongho Lee ,  Yeongkwon Ko

IPC: H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L21/4803 ,  H01L21/563 ,  H01L23/3157 ,  H01L23/367 ,  H01L23/49811 ,  H01L23/5385 ,  H01L23/562 ,  H01L24/16 ,  H01L24/73 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/73204

Abstract: A semiconductor package includes a lower substrate including a central region and an edge region, an upper substrate on the central region of the lower substrate, a first semiconductor chip on the upper substrate, a second semiconductor chip on the upper substrate and horizontally spaced apart from the first semiconductor chip, a reinforcing structure on the edge region of the lower substrate, and a molding layer that covers an inner sidewall of the reinforcing structure, a top surface of the lower substrate, a sidewall of the first semiconductor chip, a sidewall of the second semiconductor chip, and the upper substrate. The molding layer is interposed between the lower substrate and the upper substrate, between the upper substrate and the first semiconductor chip, and between the upper substrate and the second semiconductor chip. The first semiconductor chip is of a different type from the second semiconductor chip.

公开(公告)号：US11923343B2

公开(公告)日：2024-03-05

申请号：US18059747

申请日：2022-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaekyung Yoo ,  Jayeon Lee ,  Jae-eun Lee ,  Yeongkwon Ko ,  Jin-woo Park ,  Teak Hoon Lee

IPC: H01L25/065 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/13 ,  H01L23/3157 ,  H01L23/49822 ,  H01L23/49838 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586

Abstract: Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a package substrate, a first semiconductor chip mounted on the package substrate, a second semiconductor chip mounted on a top surface of the first semiconductor chip, and a first under-fill layer that fills a space between the package substrate and the first semiconductor chip. The package substrate includes a cavity in the package substrate, and a first vent hole that extends from a top surface of the package substrate and is in fluid communication with the cavity. The first under-fill layer extends along the first vent hole to fill the cavity.

公开(公告)号：US20230395403A1

公开(公告)日：2023-12-07

申请号：US18134718

申请日：2023-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo Park ,  Myungsung Kang ,  Jaekyung Yoo ,  Unbyoung Kang ,  Chungsun Lee

IPC: H01L21/67

CPC classification number: H01L21/67126

Abstract: A molding apparatus for a semiconductor package includes a chamber including a lower mold configured to hold a substrate including a plurality of molding targets, an upper mold configured to move up and down with respect to the lower mold and define a cavity between the upper mold and the lower mold, and a port configured to provide a passage communicating with the cavity, a molding material supplier configured to supply a molding material to the port, a plunger configured to pressurize the molding material inside the port, a plunger actuator configured to apply a first pressure to the plunger such that the molding material provided in the port is supplied to the cavity, and a mold actuator configured to control actuation of the upper mold. The plunger actuator is configured to supply the molding material to the cavity by applying the first pressure to the plunger, and the mold actuator is configured to pressurize the molding material in the cavity by applying a second pressure to the upper mold. The mold apparatus further includes a controller configured to control the plunger actuator to reduce the first pressure applied to the plunger after the mold actuator begins applying the second pressure to the upper mold.

公开(公告)号：US11462462B2

公开(公告)日：2022-10-04

申请号：US16787107

申请日：2020-02-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaekyung Yoo ,  Jaeeun Lee ,  Yeongkwon Ko ,  Teakhoon Lee

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56 ,  H01L25/18 ,  H01L21/48 ,  H01L25/00

Abstract: Semiconductor packages may include a semiconductor chip including a chip pad and a lower redistribution that includes a lower redistribution insulating layer and a lower redistribution pattern. The lower redistribution insulating layer may include a top surface facing the semiconductor chip. The semiconductor packages may also include a molding layer on a side of the semiconductor chip and including a bottom surface facing the lower redistribution structure and a conductive post in the molding layer. The conductive post may include a bottom surface contacting the lower redistribution. The top surface of the lower redistribution insulating layer may be closer to a top surface of the conductive post than a top surface of the molding layer. A roughness of the top surface of the molding layer may be greater than a roughness of the top surface of the conductive post.

公开(公告)号：US12165991B2

公开(公告)日：2024-12-10

申请号：US18162878

申请日：2023-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongkwon Ko ,  Un-Byoung Kang ,  Jaekyung Yoo ,  Teak Hoon Lee

IPC: H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor package including a package substrate, a connection substrate on the package substrate and having on a lower corner of the connection substrate a recession that faces a top surface of the package substrate, a semiconductor chip on the connection substrate, a plurality of first connection terminals connecting the connection substrate to the semiconductor chip, and a plurality of second connection terminals connecting the package substrate to the connection substrate. The recession is laterally spaced apart from the second connection terminals.

公开(公告)号：US20240203945A1

公开(公告)日：2024-06-20

申请号：US18419399

申请日：2024-01-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeongkwon Ko ,  Jinwoo Park ,  Jaekyung Yoo ,  Teakhoon Lee

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L23/295 ,  H01L23/3135 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/50 ,  H01L24/05 ,  H01L24/06 ,  H01L24/17 ,  H01L24/33 ,  H01L24/73 ,  H01L24/92 ,  H01L25/18 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/17181 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92143 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06586

Abstract: A semiconductor package includes a package substrate on which a base chip is disposed. A first semiconductor chip is disposed on the base chip. A second semiconductor chip is disposed on the first semiconductor chip. An inner mold layer surrounds an upper surface of the base chip and respective side surfaces of the first semiconductor chip and the second semiconductor chip. A first outer mold layer is interposed between the package substrate and the base chip while covering at least a portion of a side surface of the base chip. A second outer mold layer is disposed on the first outer mold layer while covering at least a portion of a side surface of the inner mold layer. The second outer mold layer is spaced apart from the package substrate. The first outer mold layer and the second outer mold layer have different viscosities.

公开(公告)号：US20240088092A1

公开(公告)日：2024-03-14

申请号：US18462610

申请日：2023-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaekyung Yoo ,  Woohyeong Kim ,  Jinwoo Park ,  Jayeon Lee ,  Chungsun Lee

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L25/0652 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5383 ,  H01L24/16 ,  H01L2224/16227

Abstract: A semiconductor package includes a redistribution substrate having a first surface including first and a second regions and a second surface opposite to the first surface, and including a first redistribution layer, first and second semiconductor chips positioned in a first direction on the first region the redistribution substrate, each of the first and second semiconductor chips being electrically connected to the first redistribution layer, a first molding layer on the first region on the first and second semiconductor chips, a redistribution structure on the first molding layer and including a second redistribution layer, conductive posts on the first region and electrically connecting the first redistribution layer to the second redistribution layer, third and fourth semiconductor chips positioned in a second direction, intersecting the first direction, and each electrically connected to the second redistribution layer, and a second molding layer on the second region the redistribution substrate and on the third and fourth semiconductor chips.