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    METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGES
    1.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGES 有权

    公开(公告)号：US20240404931A1

    公开(公告)日：2024-12-05

    申请号：US18436993

    申请日：2024-02-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyejin LEE ,  Jihye SHIN ,  Kihyun KIM

    IPC: H01L23/498 ,  H01L21/027 ,  H01L21/311 ,  H01L23/00 ,  H01L25/065 ,  H10B80/00

    Abstract: A method includes: forming a first photoresist layer on a first insulating layer; forming a first photoresist pattern having first opening patterns using a first exposure mask; etching the first insulating layer using the first photoresist pattern to form first via holes; removing the first photoresist pattern; forming a second photoresist layer on the first insulating layer; forming a second photoresist pattern having second opening patterns using a second exposure mask; etching the first insulating layer using the second photoresist pattern to form second via holes; removing the first photoresist pattern; forming a redistribution wiring layer on the first insulating layer, the redistribution wiring layer having first redistribution wirings connected to first bonding pads under the first insulating layer through the via holes; and mounting a semiconductor chip on the redistribution wiring layer, the semiconductor chip comprising chip pads connected to the first redistribution wirings.

    SCANNING ELECTRON MICROSCOPE (SEM) MEASUREMENT METHOD AND APPARATUS
    2.
    发明公开
    SCANNING ELECTRON MICROSCOPE (SEM) MEASUREMENT METHOD AND APPARATUS 审中-公开

    公开(公告)号：US20240079206A1

    公开(公告)日：2024-03-07

    申请号：US18301568

    申请日：2023-04-17

    Applicant: Samsung Electronics Co., Ltd

    Inventor： Kihyun KIM

    IPC: H01J37/28 ,  H01J37/22

    CPC classification number: H01J37/28 ,  H01J37/222 ,  H01J2237/2817

    Abstract: There are provided a scanning electron microscope (SEM) measurement method and/or apparatus that reduce critical dimension (CD) dispersion according to position correction of a measurement area in CD measurement in several SEM images of the same pattern. The SEM measurement method includes obtaining individual SEM images at a plurality of locations on a wafer via an SEM, generating a merged SEM image by aligning the individual SEMs and merging the individual SEM images, generating a merged measurement area in the merged SEM image, generating, in the individual SEM images, individual measurement areas corresponding to the merged measurement area, and measuring individual critical dimensions (CDs) in the individual measurement areas.

    REFRIGERATOR
    3.
    发明公开
    REFRIGERATOR 审中-公开

    公开(公告)号：US20240053085A1

    公开(公告)日：2024-02-15

    申请号：US18384621

    申请日：2023-10-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kihyun KIM ,  Seokjun SON ,  Ilsung BAE ,  Byungkwan YANG ,  Sungi HONG ,  Bongjun KWON ,  Jaehyun LEE

    IPC: F25D17/06

    CPC classification number: F25D17/065

    Abstract: A refrigerator includes: a main body; a storage compartment provided in the main body; and an air duct provided in the storage compartment and configured to discharge air into the storage compartment, wherein the air duct may include: a front panel having an assembly groove formed at upper portion of a front surface of the front panel; an air flow path part provided at a rear surface of the front panel; an air duct cover including an upper portion inserted into the assembly groove and a lower portion attached to the front panel; and a fixing member configured to detachably attach the air duct to the front panel.

    MEMORY DEVICE AND TEST METHOD THEREOF
    6.
    发明申请
    MEMORY DEVICE AND TEST METHOD THEREOF 有权

    公开(公告)号：US20210313001A1

    公开(公告)日：2021-10-07

    申请号：US17073682

    申请日：2020-10-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sungik JANG ,  Kihyun KIM ,  Soojin ANN ,  Chungki Lee ,  Dongguk HAN

    IPC: G11C29/38 ,  G11C29/44 ,  G11C11/4091 ,  H01L25/065

    Abstract: A memory device includes: a plurality of sense amplifier circuits sensing a data bit in response to a parallel test signal from a plurality of banks; a plurality of comparators comparing the data bit from each of the plurality of sense amplifier circuits with a test bit; and a logic circuit receiving output signals of the plurality of comparators and outputting a test result, wherein each of the plurality of comparators receives the test bit, an evolved parallel bit test (PBT) signal, at least one test ignore signal, and a test pass signal, and compares the data bit and the test bit in response to the evolved parallel bit test (PBT) signal, the at least one logic state test setting signal, and the test pass signal, and passes a corresponding bank regardless of a test operation in response to the test pass signal.

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