-
公开(公告)号：US10886002B1
公开(公告)日：2021-01-05
申请号：US16440212
申请日：2019-06-13
Applicant: SanDisk Technologies LLC
Inventor： Daniel Linnen , Avinash Rajagiri , Yuvaraj Krishnamoorthy , Srikar Peesari , Ashish Ghai , Dongxiang Liao
Abstract: A method for detecting defects in a memory system includes receiving a command to perform a standard erase operation on at least one memory cell of the memory system. The method also includes performing a first defect detection operation on the at least one memory cell. The method also includes setting, in response to the first defect detection operation detecting a defect, a defect status indicator. The method also includes performing the standard erase operation on the at least one memory cell. The method also includes performing a second defect detection operation on the at least one memory cell. The method also includes setting, in response to the second defect detection operation detecting a defect, the defect status indicator.
-
公开(公告)号：US20190129861A1
公开(公告)日：2019-05-02
申请号：US15799643
申请日：2017-10-31
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Daniel Linnen , Srikar Peesari , Kirubakaran Periyannan , Avinash Rajagiri , Shantanu Gupta , Jagdish Sabde , Ashish Ghai , Deepak Bharadwaj
CPC classification number: G06F12/10 , G06F3/0604 , G06F3/064 , G06F3/0656 , G06F3/0679 , G06F2212/1044 , G06F2212/2022 , G06F2212/657 , G11C5/02 , G11C7/1039 , G11C8/06 , G11C11/16 , G11C11/1653 , G11C11/1675 , G11C13/0004 , G11C13/0023 , G11C13/0069 , G11C16/0408 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C2207/107
Abstract: A partial memory die comprises a memory structure that includes a first plane of non-volatile memory cells and a second plane of non-volatile memory cells. The second plane of non-volatile memory cells is incomplete. A first buffer is connected to the first plane. A second buffer is connected to the second plane. A data path circuit is connected to an input interface, the first buffer and the second buffer. The data path circuit is configured to map data received at the input interface and route the mapped data to either the first buffer or the second buffer. An inter-plane re-mapping circuit is connected to the first buffer and the second buffer, and is configured to re-map data from the first buffer and store the re-mapped data in the second buffer for programming into the second plane.
-
3.发明授权公开(公告)号：US10991447B2
公开(公告)日：2021-04-27
申请号：US16451421
申请日：2019-06-25
Applicant: SanDisk Technologies LLC
Inventor： Daniel Linnen , Avinash Rajagiri , Dongxiang Liao , Kirubakaran Periyannan
Abstract: A method for detecting faults in a memory system includes performing an operation on at least one memory cell of the memory system. The method also includes receiving, during performance of the operation, a first clock cycle count for a first pulse of a charge pump associated with the at least one memory cell. The method also includes receiving, during performance of the operation, a second clock cycle count for a second pulse of the charge pump. The method also includes determining whether a fault will occur based on a difference between the first clock cycle count and the second clock cycle count.
-
公开(公告)号：US20190130978A1
公开(公告)日：2019-05-02
申请号：US15799666
申请日：2017-10-31
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Daniel Linnen , Srikar Peesari , Kirubakaran Periyannan , Avinash Rajagiri , Shantanu Gupta , Jagdish Sabde , Ashish Ghai , Deepak Bharadwaj , Sukhminder Singh Lobana , Shrikar Bhagath
IPC: G11C16/10 , G11C16/04 , H01L27/11529 , H01L27/11573
Abstract: A partial memory die is missing one or more components. One example of a partial memory die includes an incomplete memory structure such that the partial memory die is configured to successfully perform programming, erasing and reading of the incomplete memory structure.
-
公开(公告)号：US20210280559A1
公开(公告)日：2021-09-09
申请号：US16808128
申请日：2020-03-03
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Daniel Linnen , Kirubakaran Periyannan , Jayavel Pachamuthu , Narendhiran CR , Jay Dholakia , Everett Lyons, IV , Hoang Huynh , Dat Dinh
IPC: H01L25/065 , H01L23/00 , H01L23/525
Abstract: A fractured semiconductor die is disclosed, together with a semiconductor device including the fractured semiconductor die. During fabrication of the semiconductor dies in a wafer, the wafer may be scored in a series of parallel scribe lines through portions of each row of semiconductor dies. The scribe lines then propagate through the full thickness of the wafer to fracture off a portion of each of the semiconductor dies. It may happen that electrical traces such as bit lines in the memory cell arrays short together during the die fracture process. These electrical shorts may be cleared by running a current through each of the electrical traces.
-
Patent Agency Ranking
公开(公告)号：US20180350445A1
公开(公告)日：2018-12-06
申请号：US15610119
申请日：2017-05-31
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Daniel Linnen , Srikar Peesari , Kirubakaran Periyannan , Shantanu Gupta , Avinash Rajagiri , Dongxiang Liao , Jagdish Sabde , Rajan Paudel
CPC classification number: G11C29/1201 , G11C7/10 , G11C7/22
Abstract: Techniques are presented for testing the high-speed data path between the IO pads and the read/write buffer of a memory circuit without the use of an external test device. In an on-chip process, a data test pattern is transferred at a high data rate between the read/write register and a source for the test pattern, such as register for this purpose or the read/write buffer of another plane. The test data after the high-speed transfer is then checked against its expected, uncorrupted value, such as by transferring it back at a lower speed for comparison or by transferring the test data a second time, but at a lower rate, and comparing the high transfer rate copy with the lower transfer rate copy at the receiving end of the transfers.
-
公开(公告)号：US11195820B2
公开(公告)日：2021-12-07
申请号：US16808128
申请日：2020-03-03
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Daniel Linnen , Kirubakaran Periyannan , Jayavel Pachamuthu , Narendhiran Cr , Jay Dholakia , Everett Lyons, IV , Hoang Huynh , Dat Dinh
IPC: H01L23/00 , H01L25/065 , H01L23/525
Abstract: A fractured semiconductor die is disclosed, together with a semiconductor device including the fractured semiconductor die. During fabrication of the semiconductor dies in a wafer, the wafer may be scored in a series of parallel scribe lines through portions of each row of semiconductor dies. The scribe lines then propagate through the full thickness of the wafer to fracture off a portion of each of the semiconductor dies. It may happen that electrical traces such as bit lines in the memory cell arrays short together during the die fracture process. These electrical shorts may be cleared by running a current through each of the electrical traces.
-
公开(公告)号：US11139276B2
公开(公告)日：2021-10-05
申请号：US16808128
申请日：2020-03-03
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Daniel Linnen , Kirubakaran Periyannan , Jayavel Pachamuthu , Narendhiran Cr , Jay Dholakia , Everett Lyons, IV , Hoang Huynh , Dat Dinh
IPC: H01L23/00 , H01L25/065 , H01L23/525
Abstract: A fractured semiconductor die is disclosed, together with a semiconductor device including the fractured semiconductor die. During fabrication of the semiconductor dies in a wafer, the wafer may be scored in a series of parallel scribe lines through portions of each row of semiconductor dies. The scribe lines then propagate through the full thickness of the wafer to fracture off a portion of each of the semiconductor dies. It may happen that electrical traces such as bit lines in the memory cell arrays short together during the die fracture process. These electrical shorts may be cleared by running a current through each of the electrical traces.
-
公开(公告)号：US10776277B2
公开(公告)日：2020-09-15
申请号：US15799643
申请日：2017-10-31
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Daniel Linnen , Srikar Peesari , Kirubakaran Periyannan , Avinash Rajagiri , Shantanu Gupta , Jagdish Sabde , Ashish Ghai , Deepak Bharadwaj
IPC: G06F12/10 , G06F3/06 , G11C16/04 , G11C13/00 , G11C11/16 , G11C16/08 , G11C5/02 , G11C16/10 , G11C8/06 , G11C7/10
Abstract: A partial memory die comprises a memory structure that includes a first plane of non-volatile memory cells and a second plane of non-volatile memory cells. The second plane of non-volatile memory cells is incomplete. A first buffer is connected to the first plane. A second buffer is connected to the second plane. A data path circuit is connected to an input interface, the first buffer and the second buffer. The data path circuit is configured to map data received at the input interface and route the mapped data to either the first buffer or the second buffer. An inter-plane re-mapping circuit is connected to the first buffer and the second buffer, and is configured to re-map data from the first buffer and store the re-mapped data in the second buffer for programming into the second plane.
-
公开(公告)号：US10242750B2
公开(公告)日：2019-03-26
申请号：US15610119
申请日：2017-05-31
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Daniel Linnen , Srikar Peesari , Kirubakaran Periyannan , Shantanu Gupta , Avinash Rajagiri , Dongxiang Liao , Jagdish Sabde , Rajan Paudel
Abstract: Techniques are presented for testing the high-speed data path between the IO pads and the read/write buffer of a memory circuit without the use of an external test device. In an on-chip process, a data test pattern is transferred at a high data rate between the read/write register and a source for the test pattern, such as register for this purpose or the read/write buffer of another plane. The test data after the high-speed transfer is then checked against its expected, uncorrupted value, such as by transferring it back at a lower speed for comparison or by transferring the test data a second time, but at a lower rate, and comparing the high transfer rate copy with the lower transfer rate copy at the receiving end of the transfers.
-
-
-
-
-
-
-
-
-
Search Results
12
records
(took 0.017 seconds)
