公开(公告)号：US20170309340A1

公开(公告)日：2017-10-26

申请号：US15628417

申请日：2017-06-20

Applicant: SanDisk Technologies LLC

Inventor： Grishma Shah ,  Yan Li ,  Jian Chen ,  Kenneth Louie ,  Nian Niles Yang

IPC: G11C16/26 ,  H01L27/11556 ,  G11C11/56 ,  G06F12/0802 ,  H01L27/11582 ,  G11C16/04

CPC classification number: G11C7/1009 ,  G11C7/1015 ,  G11C7/1039 ,  G11C7/1063 ,  G11C11/56 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C2211/563 ,  G11C2216/20

Abstract: Read operations are performed in a multi-plane memory device. A state machine interfaces an external controller to each plane of memory cells to allow reading from selected word lines in the planes. In one approach, different types of read operations are performed in different planes, such as a multi-level cell read, e.g., a lower, middle or upper page read and a single-level cell (SLC) read. When the read operation in one plane uses fewer read voltages than another plane, the read data can be output early from the one plane while read operations continue on the other plane. The external controller can also command a cache release for one plane after outputting data from the caches of another plane. Read voltages can be set for each plane in a respective set of registers.

公开(公告)号：US20180197586A1

公开(公告)日：2018-07-12

申请号：US15625848

申请日：2017-06-16

Applicant: SanDisk Technologies LLC

Inventor： Qui Nguyen ,  Alexander Chu ,  Kenneth Louie ,  Anirudh Amarnath ,  Jixin Yu ,  Yen-Lung Jason Li ,  Tai-Yuan Tseng ,  Jong Yuh

IPC: G11C8/08 ,  G11C5/06 ,  H01L27/112 ,  G11C8/10 ,  G06F13/40

CPC classification number: G11C8/08 ,  G06F13/4072 ,  G11C5/06 ,  G11C8/10 ,  G11C8/14 ,  G11C16/08 ,  H01L27/112 ,  H01L27/11575 ,  H01L27/11582

Abstract: Apparatuses, systems, and methods are disclosed for three-dimensional non-volatile memory. A stack of word line layers includes word lines for a three-dimensional non-volatile memory array. A stack of word line layers may include a plurality of tiers. Word line switch transistors transfer word line bias voltages to the word lines. Word line contact regions couple word line switch transistors to word lines. A word line contact region includes a stepped structure for a tier of word line layers. A level region separates a word line contact region for a first tier from a word line contact region for a second tier.

公开(公告)号：US09947395B2

公开(公告)日：2018-04-17

申请号：US15486512

申请日：2017-04-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kenneth Louie ,  Man Mui

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/34 ,  G11C16/08

CPC classification number: G11C11/5628 ,  G11C7/14 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/32 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3459

Abstract: Techniques are presented for the programming of a non-volatile memory in which multi-state memory cells use a charge trapping layer. When writing data onto a word lines, different data states are written individually, while programming inhibiting the other states, thereby breaking down the write operation into a number of sub-operations, one for each state to be written. This allows for improved timing and decreased power consumption.

公开(公告)号：US20170221556A1

公开(公告)日：2017-08-03

申请号：US15486512

申请日：2017-04-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kenneth Louie ,  Man Mui

IPC: G11C11/56 ,  G11C16/08 ,  G11C16/34

CPC classification number: G11C11/5628 ,  G11C7/14 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/32 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3459

Abstract: Techniques are presented for the programming of a non-volatile memory in which multi-state memory cells use a charge trapping layer. When writing data onto a word lines, different data states are written individually, while programming inhibiting the other states, thereby breaking down the write operation into a number of sub-operations, one for each state to be written. This allows for improved timing and decreased power consumption.

公开(公告)号：US20200294598A1

公开(公告)日：2020-09-17

申请号：US16352824

申请日：2019-03-14

Applicant: SanDisk Technologies LLC

Inventor： Kenneth Louie ,  Seok Tae Kim ,  Arka Ganguly ,  Qui Nguyen

IPC: G11C16/08 ,  G11C16/04

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for reducing routing signals. An apparatus includes a first block decoder circuit that senses bad block data of a first latch circuit corresponding to a first memory block and couple the bad block data onto a bus. An apparatus includes a comparator circuit that compares the bad block data against a reference, sets a bad block flag, and routes the bad block flag on a routing line across an array of storage elements. An apparatus includes a second block decoder circuit that receives the bad block flag from the routing line, determines a condition of the first memory block based on the bad block flag, and determines a generation of a block selection signal for selecting a second memory block.

公开(公告)号：US10115440B2

公开(公告)日：2018-10-30

申请号：US15625848

申请日：2017-06-16

Applicant: SanDisk Technologies LLC

Inventor： Qui Nguyen ,  Alexander Chu ,  Kenneth Louie ,  Anirudh Amarnath ,  Jixin Yu ,  Yen-Lung Jason Li ,  Tai-Yuan Tseng ,  Jong Yuh

IPC: G11C8/08 ,  G11C5/06 ,  H01L27/112 ,  G11C8/10 ,  G06F13/40

Abstract: Apparatuses, systems, and methods are disclosed for three-dimensional non-volatile memory. A stack of word line layers includes word lines for a three-dimensional non-volatile memory array. A stack of word line layers may include a plurality of tiers. Word line switch transistors transfer word line bias voltages to the word lines. Word line contact regions couple word line switch transistors to word lines. A word line contact region includes a stepped structure for a tier of word line layers. A level region separates a word line contact region for a first tier from a word line contact region for a second tier.

公开(公告)号：US09627046B2

公开(公告)日：2017-04-18

申请号：US14635918

申请日：2015-03-02

Applicant: SanDisk Technologies LLC

Inventor： Kenneth Louie ,  Man Mui

IPC: G11C16/06 ,  G11C11/56 ,  G11C16/34 ,  G11C7/14 ,  G11C16/04 ,  G11C16/10 ,  G11C16/12 ,  G11C16/32

CPC classification number: G11C11/5628 ,  G11C7/14 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/32 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3459

Abstract: Techniques are presented for the programming of a non-volatile memory in which multi-state memory cells use a charge trapping layer. When writing data onto a word lines, different data states are written individually, while programming inhibiting the other states, thereby breaking down the write operation into a number of sub-operations, one for each state to be written. This allows for improved timing and decreased power consumption.

公开(公告)号：US10255978B2

公开(公告)日：2019-04-09

申请号：US15589120

申请日：2017-05-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kenneth Louie ,  Qui Nguyen ,  Tai-yuan Tseng ,  Jong Yuh ,  Ohwon Kwon

IPC: G11C16/10 ,  G11C16/26

Abstract: This disclosure provides a method and apparatus for applying a dynamic strobe signal to a plurality of sense modules during programming of an array of memory cells, where a characteristic of the dynamic strobe signal is configured to limit a peak current level through the plurality of sense modules. An example apparatus the array of memory cells, a plurality of bit lines spanning the array of memory cells, and the plurality of sense modules connected to the bit lines. The plurality of sense modules enable sensing of states of memory cells. A controller determines the characteristic of the dynamic strobe signal, where the dynamic strobe signal is varied based on the determined characteristic.

公开(公告)号：US09490020B2

公开(公告)日：2016-11-08

申请号：US15155957

申请日：2016-05-16

Applicant: SanDisk Technologies LLC

Inventor： Kenneth Louie ,  Khanh Nguyen

IPC: G11C16/04 ,  G11C16/14 ,  G11C16/08

CPC classification number: G11C16/14 ,  G11C5/146 ,  G11C7/14 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/32

Abstract: When performing an erase on a flash type non-volatile memory with a NAND type of structure, techniques are presented for inhibiting erase on selected word lines, select lines of programmable select transistors, or some combination of these. The voltage along the selected control lines are initially ramped up by the level on a corresponding input line, but then have their voltage raised to an erase inhibit level by capacitive coupling with the well structure. The level of these input signals are ramped up with the erase voltage applied to the well structure, but with a delay based upon the coupling ratio between the control line and the well.

Abstract translation: 当对具有NAND型结构的闪存型非易失性存储器执行擦除时，提出了用于抑制所选字线上的擦除，可选择选择晶体管的选择线或这些的某些组合的技术。 沿着所选择的控制线的电压首先在对应的输入线上斜坡上升，然后通过与阱结构的电容耦合使其电压升高到擦除抑制水平。 这些输入信号的电平随着施加到阱结构的擦除电压而上升，但是基于控制线和阱之间的耦合比的延迟。

公开(公告)号：US20200265899A1

公开(公告)日：2020-08-20

申请号：US16866155

申请日：2020-05-04

Applicant: SanDisk Technologies LLC

Inventor： Kenneth Louie ,  Anirudh Amarnath

IPC: G11C16/24 ,  G11C16/26 ,  G11C16/34 ,  G11C16/30 ,  G11C16/08

Abstract: A memory device and associated techniques improve a settling time of bit lines in a memory device during a sensing operation, such as read or verify operation. Supply voltage from power supply terminals in the sense circuits is briefly toggled during a discharge of a selected bit line in response to a voltage on a selected word line being increased to a second word line level or higher. This helps to create an electrical path from the selected bit line through to a supply terminal for discharging the selected bit line such that a settling time of a voltage of the selected bit line is shortened in association with a target memory cell transitioning from a non-conductive state to a conductive state.