公开(公告)号：US12243482B2

公开(公告)日：2025-03-04

申请号：US18036221

申请日：2021-11-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hajime Kimura ,  Tatsuya Onuki

IPC: G09G3/3233

Abstract: A display device excellent in downsizing, reduction in power consumption, or layout flexibility of an arithmetic device is provided. The display device includes a pixel circuit, a driver circuit, and a functional circuit. The driver circuit has a function of outputting an image signal for performing display in the pixel circuit. The functional circuit includes a CPU including a CPU core including a flip-flop electrically connected to a backup circuit. The display device includes a first layer and a second layer. The first layer includes the driver circuit and the CPU. The second layer includes the pixel circuit and the backup circuit. The first layer includes a semiconductor layer including silicon in a channel formation region. The second layer includes a semiconductor layer including a metal oxide in a channel formation region. The CPU has a function of correcting the image signal in accordance with the amount of current flowing through the pixel circuit.

公开(公告)号：US12051924B2

公开(公告)日：2024-07-30

申请号：US17291005

申请日：2019-11-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya Onuki ,  Takayuki Ikeda ,  Shunpei Yamazaki

IPC: H02J7/00 ,  H01M10/44 ,  H01M10/48 ,  H02J50/10 ,  H01L23/522 ,  H01L29/78 ,  H01L29/786

CPC classification number: H02J7/00302 ,  H01M10/44 ,  H01M10/48 ,  H02J7/0042 ,  H02J50/10 ,  H01L23/5223 ,  H01L29/7851 ,  H01L29/7869

Abstract: A structure that includes a circuit for controlling the safe operation of a secondary battery but can overcome space limitations owing to miniaturization of the housing is provided. A charge control circuit is provided over a flexible substrate and bonded to an external surface of the secondary battery. The charge control circuit is electrically connected to at least one of two terminals of the secondary battery and controls charging. To prevent overcharge, both an output transistor of a charging circuit and a blocking switch are brought into off state substantially concurrently. Blocking two paths which connect to the battery can quickly stop charging when overcharge is detected and reduce damage to the battery owing to the overcharge.

公开(公告)号：US12015012B2

公开(公告)日：2024-06-18

申请号：US17613605

申请日：2020-05-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya Onuki ,  Takanori Matsuzaki ,  Yuki Okamoto ,  Shunpei Yamazaki

IPC: H01L27/108 ,  G11C5/06 ,  H01L25/065 ,  H01L29/786 ,  H10B12/00 ,  H01L23/00

CPC classification number: H01L25/0657 ,  G11C5/063 ,  H01L29/78693 ,  H10B12/315 ,  H10B12/50 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a silicon substrate including a first circuit, a first element layer including a second circuit, and a second element layer including a third circuit. The first circuit includes a first transistor. The second circuit includes a second transistor. The third circuit includes a memory cell. The memory cell includes a third transistor and a capacitor. The first element layer and the second element layer constitute a stacked block stacked and provided in a direction perpendicular or substantially perpendicular to a surface of the silicon substrate. A plurality of stacked blocks are stacked and provided in the direction perpendicular or substantially perpendicular to the surface of the silicon substrate. Each of the plurality of stacked blocks includes a first wiring provided in the direction perpendicular or substantially perpendicular to the surface of the silicon substrate. The plurality of stacked blocks are electrically connected to each other through the wiring.

公开(公告)号：US11996132B2

公开(公告)日：2024-05-28

申请号：US17298964

申请日：2019-11-20

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tatsuya Onuki ,  Kiyoshi Kato ,  Shunpei Yamazaki

IPC: G11C11/405 ,  G11C11/4096 ,  H01L27/12 ,  H01L29/786 ,  H10B12/00

CPC classification number: G11C11/405 ,  G11C11/4096 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/78648 ,  H01L29/7869 ,  H10B12/00

Abstract: A semiconductor device includes a first transistor one of a source and a drain of which is electrically connected to a first wiring for reading data; a second transistor one of a source and a drain of which is electrically connected to a gate of the first transistor and the other of the source and the drain of which is electrically connected to a second wiring for writing the data; and a third transistor one of a source and a drain of which is electrically connected to the gate of the first transistor and the other of the source and the drain of which is electrically connected to a capacitor for retaining electric charge corresponding to the data, and the third transistor includes a metal oxide in a channel formation region.

公开(公告)号：US11968820B2

公开(公告)日：2024-04-23

申请号：US17427934

申请日：2020-02-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya Onuki ,  Yuto Yakubo ,  Seiya Saito

IPC: G11C11/00 ,  H01L27/12 ,  H01L29/24 ,  H01L29/786 ,  H10B12/00 ,  G11C5/06 ,  G11C8/08

CPC classification number: H10B12/00 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/24 ,  H01L29/78648 ,  H01L29/7869 ,  G11C5/06 ,  G11C8/08

Abstract: A novel semiconductor device is provided. The semiconductor device includes a driver circuit and a first transistor layer to a third transistor layer. The first transistor layer includes a first memory cell including a first transistor and a first capacitor. The second transistor layer includes a second memory cell including a second transistor and a second capacitor. The third transistor layer includes a switching circuit and an amplifier circuit. The first transistor is electrically connected to a first local bit line. The second transistor is electrically connected to a second local bit line. The switching circuit has a function of selecting the first local bit line or the second local bit line and electrically connecting the selected local bit line to the amplifier circuit. The first transistor layer to the third transistor layer are provided over the silicon substrate. The third transistor layer is provided between the first transistor layer and the second transistor layer.

公开(公告)号：US11705184B2

公开(公告)日：2023-07-18

申请号：US17849894

申请日：2022-06-27

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Kiyoshi Kato ,  Takahiko Ishizu ,  Tatsuya Onuki

IPC: G11C11/24 ,  G11C11/408 ,  H01L27/12 ,  H01L29/24 ,  H01L29/786 ,  H10B99/00

CPC classification number: G11C11/4085 ,  H01L27/124 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/24 ,  H01L29/7869 ,  H01L29/78648 ,  H10B99/00

Abstract: A memory device having long data retention time and high reliability is provided. The memory device includes a driver circuit and a plurality of memory cells, the memory cell includes a transistor and a capacitor, and the transistor includes a metal oxide in a channel formation region. The transistor includes a first gate and a second gate, and in a period during which the memory cell retains data, negative potentials are applied to the first gate and the second gate of the transistor.

公开(公告)号：US11476862B2

公开(公告)日：2022-10-18

申请号：US17282098

申请日：2019-10-10

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tatsuya Onuki ,  Yuto Yakubo ,  Kiyoshi Kato ,  Seiya Saito

IPC: H03M1/00 ,  H03M1/12 ,  G01D21/00 ,  G11C27/02

Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a sensor, an amplifier circuit to which a sensor signal of the sensor is input, a sample-and-hold circuit that retains a voltage corresponding to an output signal of an amplifier input to the sample-and-hold circuit, an analog-to-digital converter circuit to which an output signal of the sample-and-hold circuit corresponding to the voltage is input, and an interface circuit. The interface circuit has a function of switching and controlling a first control period in which the sensor signal is input to the amplifier circuit and an output signal of the amplifier circuit is retained in the sample-and-hold circuit and a second control period in which a digital signal obtained by output of the voltage retained in the sample-and-hold circuit to the analog-to-digital converter circuit is output to the interface circuit. In the first control period, the analog-to-digital converter circuit is switched to stop output of the digital signal. The first control period is longer than the second control period.

公开(公告)号：US11164871B2

公开(公告)日：2021-11-02

申请号：US16643073

申请日：2018-08-29

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takanori Matsuzaki ,  Yoshinobu Asami ,  Daisuke Matsubayashi ,  Tatsuya Onuki

IPC: H01L27/105 ,  H01L27/12 ,  H01L29/786

Abstract: A first transistor, a second transistor, a capacitor, and first to third conductors are included. The first transistor includes a first gate, a source, and a drain. The second transistor includes a second gate, a third gate over the second gate, first and second low-resistance regions, and an oxide sandwiched between the second gate and the third gate. The capacitor includes a first electrode, a second electrode, and an insulator sandwiched therebetween. The first low-resistance region overlaps with the first gate. The first conductor is electrically connected to the first gate and is connected to a bottom surface of the first low-resistance region. The capacitor overlaps with the first low-resistance region. The second conductor is electrically connected to the drain. The third conductor overlaps with the second conductor and is connected to the second conductor and a side surface of the second low-resistance region.

公开(公告)号：US10984840B2

公开(公告)日：2021-04-20

申请号：US16643755

申请日：2018-09-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya Onuki ,  Takanori Matsuzaki ,  Kiyoshi Kato ,  Shunpei Yamazaki

IPC: G11C11/24 ,  G11C7/06 ,  G11C14/00

Abstract: To provide a novel semiconductor device.
The semiconductor device includes cell arrays and peripheral circuits; the cell arrays include memory cells; the peripheral circuits includes a first driver circuit, a second driver circuit, a first amplifier circuit, a second amplifier circuit, a third amplifier circuit, and a fourth amplifier circuit; the first driver circuit and the second driver circuit have a function of supplying a selection signal to the cell array; the first amplifier circuit and the second amplifier circuit have a function of amplifying a potential input from the cell array; the third amplifier circuit and the fourth amplifier circuit have a function of amplifying a potential input from the first amplifier circuit or the second amplifier circuit; the first driver circuit, the second driver circuit, the first amplifier circuit, the second amplifier circuit, the third amplifier circuit, and the fourth amplifier circuit include a region overlapping with the cell array; and the memory cells include a metal oxide in a channel formation region.

公开(公告)号：US10032492B2

公开(公告)日：2018-07-24

申请号：US15455226

申请日：2017-03-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya Onuki

IPC: G11C7/02 ,  G11C7/06 ,  G11C8/10 ,  G11C11/4097 ,  G11C11/408 ,  G11C11/4091

Abstract: A semiconductor device that is novel, is capable of high-speed operation, consumes low power, or occupies a small area is provided. The semiconductor device includes a memory portion, a control circuit, and a plurality of wirings. The memory portion includes a plurality of memory circuits. The memory circuit includes a memory cell. The memory cell is electrically connected to a wiring. A first signal that indicates the amount of data that are written to or read from the memory portion is supplied to the control circuit. The control circuit has the function of controlling the number of the wirings to which a second signal for selecting the memory cell is simultaneously supplied on the basis of the first signal.