公开(公告)号：US09142646B2

公开(公告)日：2015-09-22

申请号：US14645185

申请日：2015-03-11

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferruccio Frisina ,  Angelo Magri′ ,  Mario Giuseppe Saggio

IPC: H01L21/20 ,  H01L29/66 ,  H01L29/16 ,  H01L29/165 ,  H01L29/06 ,  H01L21/02

CPC classification number: H01L29/66666 ,  H01L21/02529 ,  H01L21/02532 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0661 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/267 ,  H01L29/402 ,  H01L29/66431 ,  H01L29/7811 ,  H01L29/7813

Abstract: An embodiment of an integrated electronic device formed in a semiconductor body delimited by a lateral surface, which includes: a substrate made of a first semiconductor material; a first epitaxial region made of a second semiconductor material, which overlies the substrate and defines a first surface; a second epitaxial region made of a third semiconductor material, which overlies the first surface and is in contact with the first epitaxial region, the third semiconductor material having a bandgap narrower than the bandgap of the second semiconductor material; an active area, extending within the second epitaxial region and housing at least one elementary electronic component; and an edge structure, arranged between the active area and the lateral surface, and including a dielectric region arranged laterally with respect to the second epitaxial region, which overlies the first surface and is in contact with the first epitaxial region.

公开(公告)号：US09070694B2

公开(公告)日：2015-06-30

申请号：US14108598

申请日：2013-12-17

Applicant: STMicroelectronics S.r.l.

Inventor： Angelo Magri′ ,  Francesco Lizio

IPC: H01L21/82 ,  H01L23/00 ,  H01L29/423 ,  H01L27/02 ,  H01L29/06 ,  H01L21/28 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L23/562 ,  H01L21/28008 ,  H01L21/82 ,  H01L27/0207 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66621 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for integrating a set of electronic devices on a wafer (100; 200a; 200b) of semiconductor material having a main surface includes forming a plurality of trenches extending into the wafer from the main surface. At least one layer of electrically insulating material is formed within each trench. At least one layer of electrically conductive material is formed within each trench superimposed on the at least one layer of insulating material. The formation of the plurality of trenches includes forming the trenches partitioned into sub-sets of trenches. The trenches of a first sub-set are oriented along a first common direction that is different from the orientation of the trenches of a second sub-set.

Abstract translation: 在具有主表面的半导体材料的晶片（100; 200a; 200b）上集成一组电子器件的方法包括从主表面形成延伸到晶片中的多个沟槽。 在每个沟槽内形成至少一层电绝缘材料。 在叠加在至少一层绝缘材料上的每个沟槽内形成至少一层导电材料层。 多个沟槽的形成包括形成划分成子集的沟槽的沟槽。 第一子集的沟槽沿着与第二子集的沟槽的取向不同的第一公共方向定向。

公开(公告)号：US08895370B2

公开(公告)日：2014-11-25

申请号：US14042041

申请日：2013-09-30

Applicant: STMicroelectronics S.R.L.

Inventor： Ferruccio Frisina ,  Giuseppe Ferla ,  Angelo Magri′

IPC: H01L21/332 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/417 ,  H01L29/861 ,  H01L29/732 ,  H01L29/739 ,  H01L21/265 ,  H01L29/08

CPC classification number: H01L29/66666 ,  H01L21/26586 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/417 ,  H01L29/41708 ,  H01L29/41716 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66128 ,  H01L29/66272 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7322 ,  H01L29/7398 ,  H01L29/7809 ,  H01L29/8611

Abstract: A vertical conduction power device includes respective gate, source and drain areas formed in an epitaxial layer on a semiconductor substrate. The respective gate, source and drain metallizations are formed by a first metallization level. The gate, source and drain terminals are formed by a second metallization level. The device is configured as a set of modular areas extending parallel to each other. Each modular area has a rectangular elongate source area perimetrically surrounded by a gate area, and a drain area defined by first and second regions. The first regions of the drain extend parallel to one another and separate adjacent modular areas. The second regions of the drain area extend parallel to one another and contact ends of the first regions of the drain area.

Abstract translation: 垂直导通功率器件包括形成在半导体衬底上的外延层中的相应的栅极，源极和漏极区域。 相应的栅极，源极和漏极金属化由第一金属化层形成。 栅极，源极和漏极端子由第二金属化层形成。 该设备被配置为彼此平行延伸的一组模块区域。 每个模块区域具有由栅极区域周边包围的矩形细长源区域和由第一和第二区域限定的漏极区域。 排水的第一区域彼此平行延伸并分开相邻的模块区域。 漏极区域的第二区域彼此平行延伸并且与漏极区域的第一区域的端部接触。

公开(公告)号：US09520468B2

公开(公告)日：2016-12-13

申请号：US14166075

申请日：2014-01-28

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Angelo Magri′ ,  Antonino Sebastiano Alessandria ,  Stefania Fortuna ,  Leonardo Fragapane

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L29/1037 ,  H01L29/405 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/4941 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

Abstract: A power device integrated on a semiconductor substrate and having a plurality of conductive bridges within a trench gate structure. In an embodiment, a semiconductor substrate includes a trench having sidewalls and a bottom, the walls and bottom are covered with a first insulating coating layer which then also includes a conductive gate structure. An embodiment provides the formation of the conductive gate structure with covering at least the sidewalls with a second conductive coating layer of a first conductive material. This results in a conductive central region of a second conductive material having a different resistivity than the first conductive material forming a plurality of conductive bridges between said second conductive coating layer and said conductive central region.

Abstract translation: 集成在半导体衬底上并在沟槽栅极结构内具有多个导电桥的功率器件。 在一个实施例中，半导体衬底包括具有侧壁和底部的沟槽，壁和底部被第一绝缘涂层覆盖，然后第一绝缘涂层还包括导电栅极结构。 一个实施例提供形成导电栅极结构，至少用第一导电材料的第二导电涂层覆盖侧壁。 这导致第二导电材料的导电中心区域具有与第一导电材料不同的电阻率，该第一导电材料在所述第二导电涂层和所述导电中心区域之间形成多个导电桥。

公开(公告)号：US08921211B2

公开(公告)日：2014-12-30

申请号：US14166522

申请日：2014-01-28

Applicant: STMicroelectronics S.r.l.

Inventor： Ferruccio Frisina ,  Mario Giuseppe Saggio ,  Angelo Magri′

IPC: H01L21/02 ,  H01L21/04 ,  H01L29/10 ,  H01L29/267 ,  H01L29/66 ,  H01L29/732 ,  H01L29/737 ,  H01L29/78 ,  H01L29/861 ,  H01L29/872 ,  H01L21/265 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16

CPC classification number: H01L29/7806 ,  H01L21/02573 ,  H01L21/046 ,  H01L21/265 ,  H01L29/0619 ,  H01L29/0821 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66068 ,  H01L29/732 ,  H01L29/7371 ,  H01L29/7802 ,  H01L29/7804 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/872

Abstract: An embodiment of a vertical-conduction integrated electronic device formed in a body of semiconductor material which includes: a substrate made of a first semiconductor material and with a first type of conductivity, the first semiconductor material having a first bandgap; an epitaxial region made of the first semiconductor material and with the first type of conductivity, which overlies the substrate and defines a first surface; and a first epitaxial layer made of a second semiconductor material, which overlies the first surface and is in direct contact with the epitaxial region, the second semiconductor material having a second bandgap narrower than the first bandgap. The body moreover includes a deep region of a second type of conductivity, extending underneath the first surface and within the epitaxial region.

Abstract translation: 形成在半导体材料体内的垂直导电集成电子器件的实施例包括：由第一半导体材料制成并具有第一导电类型的衬底，第一半导体材料具有第一带隙; 由第一半导体材料制成并且具有第一类型的导电性的外延区域，其覆盖在衬底上并限定第一表面; 以及由第二半导体材料制成的第一外延层，其覆盖在第一表面上并与外延区直接接触，第二半导体材料具有比第一带隙窄的第二带隙。 身体还包括延伸在第一表面下方和外延区域内的第二类导电性的深区域。