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    SEMICONDUCTOR DEVICE INCLUDING DELAY COMPENSATION CIRCUIT
    1.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING DELAY COMPENSATION CIRCUIT 有权

    公开(公告)号：US20230091026A1

    公开(公告)日：2023-03-23

    申请号：US17994296

    申请日：2022-11-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Anil Kavala ,  Seonkyoo Lee ,  Taesung Lee ,  Jeongdon Ihm ,  Byunghoon Jeong

    IPC: H03L7/081 ,  H03L7/085 ,  H03K5/133 ,  G11C7/22

    Abstract: A semiconductor device includes an internal clock generation circuit configured to generate an internal clock; a plurality of unit circuits configured to have a first unit circuit and a second unit circuit operating while being synchronized with an internal clock; a plurality of transfer circuits including a first transfer circuit configured to provide a first transfer path having a first delay time, and a second transfer circuit configured to provide a second transfer path having a second delay time different from the first delay time; and a delay compensation circuit configured to compare a first clock input to the first unit circuit through the first transfer path with a second clock input to the second unit circuit through the second transfer path, and to adjust the second delay time so that the adjusted second delay time matches the first delay time.

    Equalizer circuit and integrated circuit including the same
    2.
    发明授权
    Equalizer circuit and integrated circuit including the same 有权

    公开(公告)号：US10171269B2

    公开(公告)日：2019-01-01

    申请号：US15099987

    申请日：2016-04-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seon-Kyoo Lee ,  Jeong-Don Ihm ,  Anil Kavala ,  Byung-Hoon Jeong

    IPC: H04L25/03 ,  H04L7/00 ,  H04L27/01

    Abstract: An equalizer circuit may include an equalizer controller and a plurality of equalizers. The equalizer controller may prove separate sets of enable signals, delay control signals and voltage control signals to the separate equalizers based on a control signal. The equalizers provide equalizer signals to separate connection nodes between separate pairs of logic circuits. An equalizer may be selectively activated based on a received enable signal. An equalizer may include a delay control circuit and a voltage control circuit. The delay control circuit may delay a received transfer signal to generate a delayed transfer signal based on a received delay control signal. The voltage control circuit may generate an equalizer signal based on the delayed transfer signal and a received voltage control signal. The equalizer circuit may reduce inter-symbol interference in the integrated circuit based on providing the equalizer signals to the connection nodes between the logic circuits.

    Semiconductor device including delay compensation circuit
    4.
    发明授权
    Semiconductor device including delay compensation circuit 有权

    公开(公告)号：US11522550B2

    公开(公告)日：2022-12-06

    申请号：US17077891

    申请日：2020-10-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Anil Kavala ,  Seonkyoo Lee ,  Taesung Lee ,  Jeongdon Ihm ,  Byunghoon Jeong

    IPC: G11C7/22 ,  H03K5/133 ,  H03L7/081 ,  H03L7/085 ,  G11C29/02

    Abstract: A semiconductor device includes an internal clock generation circuit configured to generate an internal clock; a plurality of unit circuits configured to have a first unit circuit and a second unit circuit operating while being synchronized with an internal clock; a plurality of transfer circuits including a first transfer circuit configured to provide a first transfer path having a first delay time, and a second transfer circuit configured to provide a second transfer path having a second delay time different from the first delay time; and a delay compensation circuit configured to compare a first clock input to the first unit circuit through the first transfer path with a second clock input to the second unit circuit through the second transfer path, and to adjust the second delay time so that the adjusted second delay time matches the first delay time.

    Impedance calibration circuit and method of calibrating impedance in memory device
    6.
    发明授权
    Impedance calibration circuit and method of calibrating impedance in memory device 有权

    公开(公告)号：US11367471B2

    公开(公告)日：2022-06-21

    申请号：US17352527

    申请日：2021-06-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Anil Kavala ,  Tongsung Kim ,  Chiweon Yoon ,  Byunghoon Jeong

    IPC: G11C7/10 ,  H03K19/00 ,  H01L27/115 ,  G11C16/04

    Abstract: An impedance calibration circuit includes a first variable impedance, a second variable impedance, a third variable impedance. The first variable impedance is connected to a ZQ terminal. A first control circuit performs a first impedance calibration on the first variable impedance based on an output signal from an output of a first comparator. A second control circuit performs a second impedance calibration on the third variable impedance based on an output signal from an output of a second comparator. A first switch connects an input of the first comparator to one of the ZQ terminal and the first node. A second switch connects the output of the first comparator to one of the first and second control circuits. A third switch connects an output of the first switch to one of first and second input terminals of the first comparator and connects the reference voltage to the other.

    MEMORY SYSTEM, OPERATING METHOD OF THE MEMORY SYSTEM, AND INTERFACE CIRCUIT OF THE MEMORY SYSTEM
    7.
    发明公开
    MEMORY SYSTEM, OPERATING METHOD OF THE MEMORY SYSTEM, AND INTERFACE CIRCUIT OF THE MEMORY SYSTEM 审中-公开

    公开(公告)号：US20240257850A1

    公开(公告)日：2024-08-01

    申请号：US18426825

    申请日：2024-01-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Anil Kavala ,  Youngmin Jo ,  Jungjune Park ,  Chiweon Yoon

    IPC: G11C7/22 ,  G11C7/10

    CPC classification number: G11C7/225 ,  G11C7/1096 ,  G11C7/222

    Abstract: Provided is a memory system including a memory device including a plurality of non-volatile memories, each of the plurality of non-volatile memories being electrically connected to a buffer chip, and a memory controller electrically connected to the buffer chip and configured to transmit a reference clock signal used in correction of a data signal, wherein the buffer chip includes a delay clock generation chain configured to generate a first delay clock signal or a second delay clock signal from the reference clock signal, a first register configured to store the first delay clock signal, and a second register configured to store the second delay clock signal, and wherein the buffer chip is configured to perform compensation on a strobe signal of the data signal based on the first delay clock signal, and perform compensation on the data signal based on the second delay clock signal.

    IMPEDANCE CALIBRATION CIRCUIT AND METHOD OF CALIBRATING IMPEDANCE IN MEMORY DEVICE
    8.
    发明申请
    IMPEDANCE CALIBRATION CIRCUIT AND METHOD OF CALIBRATING IMPEDANCE IN MEMORY DEVICE 有权

    公开(公告)号：US20220148630A1

    公开(公告)日：2022-05-12

    申请号：US17352527

    申请日：2021-06-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Anil Kavala ,  Tongsung Kim ,  Chiweon Yoon ,  Byunghoon Jeong

    IPC: G11C7/10 ,  H03K19/00

    Abstract: An impedance calibration circuit includes a first variable impedance, a second variable impedance, a third variable impedance. The first variable impedance is connected to a ZQ terminal. A first control circuit performs a first impedance calibration on the first variable impedance based on an output signal from an output of a first comparator. A second control circuit performs a second impedance calibration on the third variable impedance based on an output signal from an output of a second comparator. A first switch connects an input of the first comparator to one of the ZQ terminal and the first node. A second switch connects the output of the first comparator to one of the first and second control circuits. A third switch connects an output of the first switch to one of first and second input terminals of the first comparator and connects the reference voltage to the other.

    SEMICONDUCTOR DEVICE INCLUDING DELAY COMPENSATION CIRCUIT
    9.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING DELAY COMPENSATION CIRCUIT 有权

    公开(公告)号：US20210320664A1

    公开(公告)日：2021-10-14

    申请号：US17077891

    申请日：2020-10-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Anil Kavala ,  Seonkyoo Lee ,  Taesung Lee ,  Jeongdon Ihm ,  Byunghoon Jeong

    IPC: H03L7/081 ,  G11C7/22 ,  H03K5/133 ,  H03L7/085

    Abstract: A semiconductor device includes an internal clock generation circuit configured to generate an internal clock; a plurality of unit circuits configured to have a first unit circuit and a second unit circuit operating while being synchronized with an internal clock; a plurality of transfer circuits including a first transfer circuit configured to provide a first transfer path having a first delay time, and a second transfer circuit configured to provide a second transfer path having a second delay time different from the first delay time; and a delay compensation circuit configured to compare a first clock input to the first unit circuit through the first transfer path with a second clock input to the second unit circuit through the second transfer path, and to adjust the second delay time so that the adjusted second delay time matches the first delay time.

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