公开(公告)号：US20230157022A1

公开(公告)日：2023-05-18

申请号：US17986371

申请日：2022-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook SHIN ,  Changhyun KIM ,  Sehun PARK ,  Hyunwoo KIM ,  Kyung-Eun BYUN ,  Dongjin YUN ,  Changseok LEE

IPC: H01L27/11582 ,  G06N3/063

CPC classification number: H01L27/11582 ,  G06N3/0635

Abstract: A vertical nonvolatile memory device may include a channel layer extending in a first direction; a plurality of gate electrodes and a plurality of spacers each extending in a second direction crossing the first direction, the plurality of gate electrodes and the plurality of spacers being alternately arranged with each other in the first direction; and a gate insulating layer extending in the first direction between the channel layer and the plurality of gate electrodes. Each of the plurality of gate electrodes may include a metal-doped graphene.

公开(公告)号：US20230081646A1

公开(公告)日：2023-03-16

申请号：US17902111

申请日：2022-09-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhyun KIM ,  Unki KIM ,  Alum JUNG ,  Kyung-Eun BYUN

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/161 ,  H01L29/423 ,  H01L29/775 ,  H01L21/02 ,  H01L21/306 ,  H01L29/66

Abstract: A multi bridge channel field effect transistor includes a substrate, a first source/drain pattern on the substrate, a second source/drain pattern apart from the first source/drain pattern in a first direction on the substrate, a first channel layer and a second channel layer between the first source/drain pattern and the second source/drain pattern, a first graphene barrier between the first channel layer and the first source/drain pattern, a gate insulating layer surrounding the first channel layer, and a gate electrode surrounding the first channel layer with the gate insulating layer therebetween.

公开(公告)号：US20210206643A1

公开(公告)日：2021-07-08

申请号：US17138194

申请日：2020-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changseok LEE ,  Changhyun KIM ,  Kyung-Eun BYUN ,  Keunwook SHIN ,  Hyeonjin SHIN ,  Eunkyu LEE

IPC: C01B32/186 ,  C01B32/194 ,  C23C16/02 ,  C23C16/04 ,  C23C16/26 ,  C23C16/513

Abstract: Provided is a method of selectively growing graphene. The method includes forming an ion implantation region and an ion non-implantation region by implanting ions locally into a substrate; and selectively growing graphene in the ion implantation region or the ion non-implantation region.

公开(公告)号：US20190205614A1

公开(公告)日：2019-07-04

申请号：US16163707

申请日：2018-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhyun KIM ,  Jae Mo SUNG ,  Youngwan SEO

IPC: G06K9/00 ,  G06T5/00 ,  G06T7/11 ,  H04N5/225

CPC classification number: G06K9/00201 ,  G06K9/00791 ,  G06T5/003 ,  G06T7/11 ,  G06T2207/20021 ,  G06T2207/30252 ,  H04N5/2256

Abstract: Disclosed is a method and apparatus for recognizing an object, the method including determining whether an image comprises a blur, determining a blur type of the blur based on control information of a vehicle, in response to the image comprising the blur, selecting a de-blurring scheme corresponding to the determined blur type, de-blurring the image using the selected de-blurring scheme, and recognizing an object in the image based the de-blurred image.

公开(公告)号：US20190161351A1

公开(公告)日：2019-05-30

申请号：US16183146

申请日：2018-11-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjae SONG ,  Keunwook SHIN ,  Hyeonjin SHIN ,  Changseok LEE ,  Changhyun KIM ,  Kyungeun BYUN ,  Seungwon LEE ,  Eunkyu LEE

IPC: C01B32/186 ,  H01L23/532 ,  H01L21/285 ,  H01L21/768 ,  C23C16/26 ,  C23C16/50

Abstract: Provided are nanocrystalline graphene and a method of forming the nanocrystalline graphene through a plasma enhanced chemical vapor deposition process. The nanocrystalline graphene may have a ratio of carbon having an sp2 bonding structure to total carbon within the range of about 50% to 99%. In addition, the nanocrystalline graphene may include crystals having a size of about 0.5 nm to about 100 nm.

公开(公告)号：US20180061490A1

公开(公告)日：2018-03-01

申请号：US15448998

申请日：2017-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun LEE ,  Seunggeol NAM ,  Changhyun KIM ,  Hyeonjin SHIN ,  Yeonchoo CHO ,  Jinseong HEO ,  Seongjun PARK

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: G11C13/0004 ,  G11C13/0069 ,  G11C13/0097 ,  H01L27/24 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1641

Abstract: A phase change memory device may include a phase change layer that includes a two-dimensional (2D) material. The phase change layer may include a layered structure that includes one or more layers of 2D material. The phase change layer may be provided between a first electrode and a second electrode, and the phase of at least a portion of one or more of the layers of 2D material may be changed based on an electrical signal applied to the phase change layer through the first electrode and the second electrode. The 2D material may include a chalcogenide-based material or phosphorene. The 2D material may be associated with a phase change temperature that is greater than or equal to about 200° C. and lower than or equal to about 500° C.

公开(公告)号：US20180047818A1

公开(公告)日：2018-02-15

申请号：US15439031

申请日：2017-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunggeol NAM ,  Hyeonjin SHIN ,  Yeonchoo CHO ,  Minhyun LEE ,  Changhyun KIM ,  Seongjun PARK

IPC: H01L29/40 ,  H01L29/78

CPC classification number: H01L29/408 ,  H01L21/283 ,  H01L29/41725 ,  H01L29/456 ,  H01L29/66568 ,  H01L29/78 ,  H01L29/7839 ,  H01L29/786

Abstract: A semiconductor device includes a silicon semiconductor layer including at least one region doped with a first conductive type dopant, a metal material layer electrically connected to the doped region, and a self-assembled monolayer (SAM) between the doped region and the metal material layer, the SAM forming a molecular dipole on an interface of the silicon semiconductor layer in a direction of reducing a Schottky barrier height (SBH).

公开(公告)号：US20230343846A1

公开(公告)日：2023-10-26

申请号：US18151775

申请日：2023-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook SHIN ,  Eunkyu LEE ,  Changseok LEE ,  Changhyun KIM ,  Kyung-Eun BYUN

IPC: H01L29/45

CPC classification number: H01L29/45

Abstract: A semiconductor device may include a first semiconductor layer including a first semiconductor material; a metal layer facing the first semiconductor layer and having conductivity; a 2D material layer between the first semiconductor layer and the metal layer; and a second semiconductor layer between the first semiconductor layer and the 2D material layer. The second semiconductor layer may include a second semiconductor material different from the first semiconductor material. The second semiconductor layer and the 2D material layer may be in direct contact with each other. The second semiconductor material may include germanium.

公开(公告)号：US20230207312A1

公开(公告)日：2023-06-29

申请号：US18179565

申请日：2023-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunkyu LEE ,  Kyung-Eun BYUN ,  Hyunjae SONG ,  Hyeonjin SHIN ,  Changhyun KIM ,  Keunwook SHIN ,  Changseok LEE ,  Alum JUNG

IPC: H01L21/02 ,  H01L29/16 ,  H01L29/165

CPC classification number: H01L21/02447 ,  H01L29/1606 ,  H01L29/1608 ,  H01L29/165 ,  H01L21/02499 ,  H01L21/02527 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/02381

Abstract: Provided are a graphene structure and a method of forming the graphene structure. The graphene structure includes a substrate and graphene on a surface of the substrate. Here, a bonding region in which a material of the substrate and carbon of the graphene are covalently bonded is formed between the surface of the substrate and the graphene.

公开(公告)号：US20230070355A1

公开(公告)日：2023-03-09

申请号：US17670912

申请日：2022-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook SHIN ,  Changhyun KIM ,  Kyung-Eun BYUN

IPC: H01L29/49 ,  H01L29/40 ,  H01L21/28

Abstract: Disclosed are a layer structure including a metal layer and a carbon layer, a manufacturing method the layer structure, an electronic device including the layer structure, and an electronic apparatus including the electronic device. The layer structure according to an embodiment includes an insulating layer on one surface of a semiconductor layer, a first metal layer facing the semiconductor layer with the insulating layer therebetween, a conductive first carbon layer arranged between the insulating layer and the first metal layer, the conductive first carbon layer being in contact with a first surface of the first metal layer. The first metal layer may be provided above or below the semiconductor layer. The first carbon layer may include a graphene layer. The first carbon layer may extend to another surface of the first metal layer.