公开(公告)号：US12137419B2

公开(公告)日：2024-11-05

申请号：US18143105

申请日：2023-05-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghun Heo ,  Youngduk Kim ,  Joonseok Kim ,  Dongsuk Shin

IPC: G06F1/32 ,  H04W52/02

Abstract: A power management approach for a mobile device includes comparing a battery provided power supply voltage to a reference voltage in order to generate an alarm signal. In response to the alarm signal the frequency of an operating clock applied to a system-on-chip is changed.

公开(公告)号：US12123789B2

公开(公告)日：2024-10-22

申请号：US17366348

申请日：2021-07-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungsu Kim ,  Yunhyeok Im ,  Inhwan Baek ,  Dongsuk Shin

IPC: G01K7/42 ,  G05D23/19 ,  G06F1/20 ,  G06F1/3206 ,  G06F1/3296 ,  G06F11/30 ,  G06F1/28 ,  G06F1/3237 ,  G06F1/324 ,  G06F123/02 ,  G06N20/00

CPC classification number: G01K7/425 ,  G01K7/42 ,  G05D23/19 ,  G06F1/206 ,  G06F1/3206 ,  G06F1/3296 ,  G06F11/3058 ,  G06F1/28 ,  G06F1/3237 ,  G06F1/324 ,  G06F11/3062 ,  G06F2123/02 ,  G06N20/00 ,  Y02D10/00

Abstract: The present disclosure provides a device and methods to control a temperature of an integrated circuit (IC). For example, a device may include a circuit (e.g., an IC), a power monitor, a temperature sensor, and a controller. In some examples, temperature may be estimated based on power measured by a dynamic power monitor (DPM). In some cases, the estimated temperatures may be corrected based on temperature sensed by a temperature sensor on the IC. The power may be measured in shorter time periods and/or more frequent time periods compared to a time periods that the temperature sensor senses temperature. Accordingly, the temperature of an IC may be detected and adjusted more frequently based on the power measurements, and the temperature estimates may be adjusted for accuracy based on sensed temperatures.

公开(公告)号：US12046682B2

公开(公告)日：2024-07-23

申请号：US17689322

申请日：2022-03-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ingyu Jang ,  Jinbum Kim ,  Dahye Kim ,  Sujin Jung ,  Dongsuk Shin

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/764 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/78696 ,  H01L21/0259 ,  H01L21/764 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78618

Abstract: An integrated circuit (IC) device includes a fin-type active region on a substrate. A mesa-type channel region protrudes from the fin-type active region in a vertical direction. The mesa-type channel region is integrally connected with the fin-type active region. A gate line substantially surrounds a mesa-type channel region on the fin-type active region. A gate dielectric film is between the mesa-type channel region and the gate line. The mesa-type channel region includes: a plurality of round convex portions, which are convex toward the gate line; a concavo-convex sidewall, which includes a portion of each of the plurality of round convex portions and faces the gate line; and at least one void, which is inside the mesa-type channel region.

公开(公告)号：US20230020176A1

公开(公告)日：2023-01-19

申请号：US17840819

申请日：2022-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeseoung Park ,  Wandon Kim ,  Suyoung Bae ,  Dongsoo Lee ,  Dongsuk Shin ,  Doyoung Choi

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device includes a substrate including first and second regions, first and second active patterns provided on the first and second regions, respectively, a pair of first source/drain patterns on the first active pattern and a first channel pattern therebetween, a pair of second source/drain patterns on the second active pattern and a second channel pattern therebetween, first and second gate electrodes respectively provided on the first and second channel patterns, and first and second gate insulating layers respectively interposed between the first and second channel patterns and the first and second gate electrodes. Each of the first and second gate insulating layers includes an interface layer and a first high-k dielectric layer thereon, and the first gate insulating layer further includes a second high-k dielectric layer on the first high-k dielectric layer.

公开(公告)号：US20220136909A1

公开(公告)日：2022-05-05

申请号：US17366348

申请日：2021-07-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungsu Kim ,  Yunhyeok Im ,  Inhwan Baek ,  Dongsuk Shin

IPC: G01K7/42 ,  G06F1/20 ,  G06F1/3206 ,  G06F1/3296

Abstract: The present disclosure provides a device and methods to control a temperature of an integrated circuit (IC). For example, a device may include a circuit (e.g., an IC), a power monitor, a temperature sensor, and a controller. In some examples, temperature may be estimated based on power measured by a dynamic power monitor (DPM). In some cases, the estimated temperatures may be corrected based on temperature sensed by a temperature sensor on the IC. The power may be measured in shorter time periods and/or more frequent time periods compared to a time periods that the temperature sensor senses temperature. Accordingly, the temperature of an IC may be detected and adjusted more frequently based on the power measurements, and the temperature estimates may be adjusted for accuracy based on sensed temperatures.

公开(公告)号：US20180090589A1

公开(公告)日：2018-03-29

申请号：US15820171

申请日：2017-11-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Kwan Yu ,  Kooktae Kim ,  Chanjin Park ,  Dongsuk Shin ,  Youngdal Lim ,  Sahwan Hong

IPC: H01L29/49 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/165 ,  H01L29/161 ,  H01L29/16 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/4991 ,  H01L21/7682 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L23/485 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/7848

Abstract: A semiconductor device includes a gate assembly disposed on a device isolation layer, a gate spacer disposed on a side surface of the gate assembly, a contact assembly disposed on the gate spacer, an air gap disposed between the device isolation layer and the contact assembly, and a first spacer capping layer disposed between the gate spacer and the air gap. The first spacer capping layer has an etch selectivity with respect to the gate spacer.

公开(公告)号：US20230141852A1

公开(公告)日：2023-05-11

申请号：US17866966

申请日：2022-07-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanggil Lee ,  Jungtaek Kim ,  Dohyun Go ,  Pankwi Park ,  Dongsuk Shin ,  Namkyu Cho ,  Ryong Ha ,  Yang Xu

IPC: H01L29/78 ,  H01L29/08 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L21/823814 ,  H01L27/0922

Abstract: A semiconductor device includes a semiconductor active region having a vertical stack of multiple spaced-apart semiconductor channel regions thereon. A gate electrode extends on the active region and between the spaced-apart channel regions. A source/drain region contacts the spaced-apart channel regions. The source/drain region includes a stack of at least first, second and third epitaxial layers having different electrical characteristics. The first epitaxial layer contacts the active region and each of the spaced-apart channel regions. The second epitaxial layer contacts a first portion of an upper surface of the first epitaxial layer. The third epitaxial layer contacts a second portion of the upper surface of the first epitaxial layer. Each of the first, second and third epitaxial layers includes silicon germanium (SiGe) with unequal levels of germanium (Ge) therein. A level of germanium in the third epitaxial layer exceeds a level of germanium in the second epitaxial layer, which exceeds a level of germanium in the first epitaxial layer.

公开(公告)号：US20230059169A1

公开(公告)日：2023-02-23

申请号：US17718795

申请日：2022-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinbum Kim ,  Dongmyoung Kim ,  Cheol Kim ,  Dongsuk Shin ,  Woogwan Shim ,  Seung Hun Lee ,  Soonwook Jung

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L21/8234

Abstract: A semiconductor device includes: an active pattern disposed on a substrate; a source/drain pattern disposed on the active pattern; a channel pattern connected to the source/drain pattern, wherein the channel pattern includes semiconductor patterns stacked on each other and spaced apart from each other; and a gate electrode disposed on the channel pattern and extending in a first direction, wherein the gate electrode includes: a channel neighboring part adjacent to a first sidewall of a first semiconductor pattern of the stacked semiconductor patterns; and a body part spaced apart from the first semiconductor pattern, wherein the channel neighboring part is disposed between the body part and the first semiconductor pattern, wherein the first sidewall of the first semiconductor pattern has a first width, wherein the channel neighboring part has a second width less than the first width. The body part has a third width greater than the second width.

公开(公告)号：US20230051750A1

公开(公告)日：2023-02-16

申请号：US17689322

申请日：2022-03-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ingyu Jang ,  Jinbum Kim ,  Dahye Kim ,  Sujin Jung ,  Dongsuk Shin

IPC: H01L29/786 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/764 ,  H01L29/66

Abstract: An integrated circuit (IC) device includes a fin-type active region on a substrate. A mesa-type channel region protrudes from the fin-type active region in a vertical direction. The mesa-type channel region is integrally connected with the fin-type active region. A gate line substantially surrounds a mesa-type channel region on the fin-type active region. A gate dielectric film is between the mesa-type channel region and the gate line. The mesa-type channel region includes: a plurality of round convex portions, which are convex toward the gate line; a concavo-convex sidewall, which includes a portion of each of the plurality of round convex portions and faces the gate line; and at least one void, which is inside the mesa-type channel region.

公开(公告)号：US10181525B2

公开(公告)日：2019-01-15

申请号：US15374093

申请日：2016-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghyun Roh ,  Pankwi Park ,  Dongsuk Shin ,  Chulwoong Lee ,  Nae-in Lee

IPC: H01L29/78 ,  H01L21/306 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L21/762 ,  H01L29/165 ,  H01L21/8234 ,  H01L29/161

Abstract: According to embodiments of the inventive concept, a gate electrode is formed on a substrate, and a first spacer, a second spacer, and a third spacer are sequentially formed on a sidewall of the gate electrode. The substrate is etched to form a recess region. A compressive stress pattern is formed in the recess region. A protective spacer is formed on a sidewall of the third spacer. When the recess region is formed, a lower portion of the second spacer is removed to form a gap region between the first and third spacers. The protective spacer fills the gap region.