公开(公告)号：US20240234377A9

公开(公告)日：2024-07-11

申请号：US18536332

申请日：2023-12-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinnam KIM ,  Seokho KIM ,  Hoonjoo NA ,  Kwangjin MOON

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L24/05 ,  H01L24/08 ,  H01L24/16 ,  H01L24/48 ,  H01L25/18 ,  H01L2224/05147 ,  H01L2224/08145 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2225/06541

Abstract: A semiconductor package includes a first structure including a first semiconductor chip comprising a first semiconductor integrated circuit, and a second structure on the first structure. The second structure includes a second semiconductor chip including a second semiconductor integrated circuit, a semiconductor pattern horizontally spaced apart from the second semiconductor chip and on a side surface of the second semiconductor chip, an insulating pattern between the second semiconductor chip and the semiconductor pattern, and through-electrode structures. At least one of the through-electrode structures penetrates through at least a portion of the second semiconductor chip or penetrates through the semiconductor pattern. The semiconductor pattern has a first side surface facing the side surface of the second semiconductor chip and a second side surface opposing the first side surface. The second side surface of the semiconductor pattern is vertically aligned with a side surface of the first semiconductor chip.

公开(公告)号：US20240136334A1

公开(公告)日：2024-04-25

申请号：US18536332

申请日：2023-12-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinnam KIM ,  Seokho KIM ,  Hoonjoo NA ,  Kwangjin MOON

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L24/05 ,  H01L24/08 ,  H01L24/16 ,  H01L24/48 ,  H01L25/18 ,  H01L2224/05147 ,  H01L2224/08145 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2225/06541

Abstract: A semiconductor package includes a first structure including a first semiconductor chip comprising a first semiconductor integrated circuit, and a second structure on the first structure. The second structure includes a second semiconductor chip including a second semiconductor integrated circuit, a semiconductor pattern horizontally spaced apart from the second semiconductor chip and on a side surface of the second semiconductor chip, an insulating pattern between the second semiconductor chip and the semiconductor pattern, and through-electrode structures. At least one of the through-electrode structures penetrates through at least a portion of the second semiconductor chip or penetrates through the semiconductor pattern. The semiconductor pattern has a first side surface facing the side surface of the second semiconductor chip and a second side surface opposing the first side surface. The second side surface of the semiconductor pattern is vertically aligned with a side surface of the first semiconductor chip.

公开(公告)号：US20220068852A1

公开(公告)日：2022-03-03

申请号：US17501133

申请日：2021-10-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Il CHOI ,  Pil-Kyu KANG ,  Hoechul KIM ,  Hoonjoo NA ,  Jaehyung PARK ,  Seongmin SON

IPC: H01L23/00 ,  H01L25/16 ,  H01L27/146 ,  H01L23/31

Abstract: A semiconductor device and a semiconductor package, the device including a first buffer dielectric layer on a first dielectric layer; a second dielectric layer and a second buffer dielectric layer sequentially disposed on the first buffer dielectric layer, the second buffer dielectric layer being in contact with the first buffer dielectric layer; and a pad interconnection structure that penetrates the first buffer dielectric layer and the second buffer dielectric layer, wherein the pad interconnection structure includes copper and tin.

公开(公告)号：US20250062262A1

公开(公告)日：2025-02-20

申请号：US18934371

申请日：2024-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoonjoo NA ,  Jungseob SO ,  Taeseong KIM ,  Sohye CHO ,  Sonkwan HWANG

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: The semiconductor device includes a lower chip structure including a peripheral circuit, a first memory chip structure on the lower chip structure, and a second memory chip structure on the first memory chip structure. The first memory chip structure includes a first stack structure and a first vertical memory structure. The first stack structure includes first gate lines stacked in a vertical direction and extending in a first horizontal direction. The first vertical memory structure penetrates through the first gate lines in the vertical direction. The second memory chip structure includes a second stack structure and a second vertical memory structure. The second stack structure includes second gate lines stacked in the vertical direction and extending in a second horizontal direction, perpendicular to the first horizontal direction. The second vertical memory structure penetrates through the second gate lines in the vertical direction.

公开(公告)号：US20230170296A1

公开(公告)日：2023-06-01

申请号：US17961056

申请日：2022-10-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Anthony Dongick LEE ,  Sangcheol NA ,  Kichul PARK ,  Doohwan PARK ,  Kyoungwoo LEE ,  Rakhwan KIM ,  Yoonsuk KIM ,  Jinnam KIM ,  Hoonjoo NA ,  Eunji JUNG ,  Juyoung JUNG

IPC: H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L23/53238 ,  H01L23/53223 ,  H01L23/53266

Abstract: A semiconductor device includes a substrate. A wiring layer is over the substrate. A first via structure directly contacts a lower portion of the wiring layer. A second via structure directly contacts an upper portion of the wiring layer. The first via structure generates first stress in the wiring layer. The second via structure generates second stress in the wiring layer. The second stress is of an opposite type to the first stress. The first stress and the second stress compensate for each other in the wiring layer.

公开(公告)号：US20220310485A1

公开(公告)日：2022-09-29

申请号：US17514218

申请日：2021-10-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sonkwan HWANG ,  Taeseong KIM ,  Hoonjoo NA ,  Kwangjin MOON ,  Hyungjun JEON

IPC: H01L23/48 ,  H01L23/528 ,  H01L27/088 ,  H01L25/065 ,  H01L21/768

Abstract: A semiconductor device including a semiconductor substrate, an integrated circuit layer on the semiconductor substrate, first to nth metal wiring layers (where n is a positive integer) sequentially stacked on the semiconductor substrate and the integrated circuit layer, a first through via structure extending in a vertical direction toward the semiconductor substrate from a first via connection metal wiring layer, which is one of the second to nth metal wiring layers other than the first metal wiring layer, and passing through the semiconductor substrate, and a second through via structure being apart from the first through via structure, extending in a vertical direction toward the semiconductor substrate from a second via connection metal wiring layer, which is one of the second to nth metal wiring layers other than the first metal wiring layer, and passing through the semiconductor substrate may be provided.

公开(公告)号：US20170005175A1

公开(公告)日：2017-01-05

申请号：US15186982

申请日：2016-06-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeyeol SONG ,  Wandon KIM ,  Hoonjoo NA ,  Suyoung BAE ,  Hyeok-Jun SON ,  Sangjin HYUN

IPC: H01L29/51 ,  H01L29/423 ,  H01L29/78 ,  H01L27/085

CPC classification number: H01L29/517 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823462 ,  H01L27/085 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518

Abstract: A semiconductor device includes a semiconductor substrate including multiple active regions having a common conductivity type and separate, respective gate electrodes on the separate active regions. Different high-k dielectric layers may he between the separate active regions and the respective gate electrodes on the active regions. Different quantities of high-k dielectric layers may be between the separate active regions and the respective gate electrodes on the active regions. The different high-k dielectric layers may include different work-function adjusting materials.

Abstract translation: 半导体器件包括半导体衬底，该半导体衬底包括具有共同导电类型的多个有源区和在分离的有源区上分开的相应的栅电极。 不同的高k电介质层可以在分离的有源区和有源区上的相应栅电极之间。 不同数量的高k电介质层可以在分离的有源区域和有源区域上的相应栅电极之间。 不同的高k电介质层可以包括不同的功函调整材料。

公开(公告)号：US20250038141A1

公开(公告)日：2025-01-30

申请号：US18916136

申请日：2024-10-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joohee JANG ,  Seokho KIM ,  Hoonjoo NA ,  Jaehyung PARK ,  Kyuha LEE

IPC: H01L23/00 ,  H01L27/146

Abstract: A method includes forming a first substrate including a first dielectric layer and a first metal pad, forming a second substrate including a second dielectric layer and a second metal pad, and bonding the first dielectric layer to the second dielectric layer, and the first metal pad to the second metal pad. One or both of the first and second substrates is formed by forming a first insulating layer, forming an opening in the layer, forming a barrier on an inner surface of the opening, forming a metal pad material on the barrier, polishing the metal pad material to expose a portion of the barrier and to form a gap, expanding the gap, forming a second insulating layer to fill the opening and the gap, and polishing the insulating layers such that a top surface of the metal pad is substantially planar with an upper surface of the polished layer.

公开(公告)号：US20250022823A1

公开(公告)日：2025-01-16

申请号：US18904203

申请日：2024-10-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il CHOI ,  Pil-Kyu KANG ,  Hoechul KIM ,  Hoonjoo NA ,  Jaehyung PARK ,  Seongmin SON

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/16 ,  H01L27/146

Abstract: A semiconductor device and a semiconductor package, the device including a first buffer dielectric layer on a first dielectric layer; a second dielectric layer and a second buffer dielectric layer sequentially disposed on the first buffer dielectric layer, the second buffer dielectric layer being in contact with the first buffer dielectric layer; and a pad interconnection structure that penetrates the first buffer dielectric layer and the second buffer dielectric layer, wherein the pad interconnection structure includes copper and tin.

公开(公告)号：US20230361004A1

公开(公告)日：2023-11-09

申请号：US18354068

申请日：2023-07-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sonkwan HWANG ,  Taeseong KIM ,  Hoonjoo NA ,  Kwangjin MOON ,  Hyungjun JEON

IPC: H01L23/48 ,  H01L27/088 ,  H01L25/065 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/481 ,  H01L27/0886 ,  H01L25/0657 ,  H01L21/76898 ,  H01L23/528 ,  H01L2224/0603 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L24/06

Abstract: A semiconductor device including a semiconductor substrate, an integrated circuit layer on the semiconductor substrate, first to nth metal wiring layers (where n is a positive integer) sequentially stacked on the semiconductor substrate and the integrated circuit layer, a first through via structure extending in a vertical direction toward the semiconductor substrate from a first via connection metal wiring layer, which is one of the second to nth metal wiring layers other than the first metal wiring layer, and passing through the semiconductor substrate, and a second through via structure being apart from the first through via structure, extending in a vertical direction toward the semiconductor substrate from a second via connection metal wiring layer, which is one of the second to nth metal wiring layers other than the first metal wiring layer, and passing through the semiconductor substrate may be provided.