公开(公告)号：US20160064804A1

公开(公告)日：2016-03-03

申请号：US14840583

申请日：2015-08-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Young KIM ,  Yoon-Jae LEE ,  In-Young LEE ,  Won-Seok JEONG ,  Sang-Hoon CHOI ,  Brian CHEON

IPC: H01Q1/27 ,  H01Q1/24 ,  H01Q7/00

CPC classification number: H01Q1/273 ,  G04G21/04 ,  G04R60/06 ,  H01Q1/243 ,  H01Q5/371 ,  H01Q7/00 ,  H01Q15/008

Abstract: An antenna device implemented to prevent the deterioration in radiation performance due to a metal mechanical part and an electronic device including the same is provided. The electronic device includes a metal member in a shape of a loop that is disposed in at least one area of the electronic device and a substrate (printed circuit board (PCB)) for supplying power to a preset location of the metal member in order to use the metal member as an antenna radiator, wherein at least one location of the metal member that differs from the power-supplied location is grounded through the substrate.

Abstract translation: 提供了一种实现用于防止由于金属机械部件引起的辐射性能劣化的天线装置和包括其的电子设备。 电子设备包括设置在电子设备的至少一个区域中的环形金属构件和用于向金属构件的预设位置供电的衬底（印刷电路板（PCB）），以便 使用金属构件作为天线辐射器，其中与供电位置不同的金属构件的至少一个位置通过基板接地。

公开(公告)号：US20160124396A1

公开(公告)日：2016-05-05

申请号：US14928510

申请日：2015-10-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Hoon CHOI ,  Tae-Young KIM ,  Yoon-Jae LEE ,  In-Young LEE ,  Won-Seok JEONG ,  Brian CHEON

IPC: G04G17/08 ,  G04B37/00 ,  G04G21/08 ,  G04G21/04 ,  H01Q1/24 ,  H01Q1/27

CPC classification number: G04G17/08 ,  G04B37/0008 ,  G04G17/04 ,  G04G21/04 ,  G04G21/08 ,  G04R60/10 ,  H01Q1/243 ,  H01Q1/273 ,  H01Q9/42

Abstract: An electronic device is provided. The electronic device includes a housing comprising a recess portion formed along an edge of the housing, a sealing member arranged in the recess portion, so as to provide a seal between structures coupled with the housing, an antenna member disposed in at least a portion of the sealing member, and a substrate electrically connected with the antenna member.

Abstract translation: 提供电子设备。 电子设备包括壳体，其包括沿着壳体的边缘形成的凹部，布置在凹部中的密封构件，以便在与壳体联接的结构之间提供密封，天线构件设置在至少一部分 密封构件和与天线构件电连接的基板。

公开(公告)号：US20150069635A1

公开(公告)日：2015-03-12

申请号：US14463650

申请日：2014-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonkeun KIM ,  In-Young LEE ,  Chang-Seong JEON ,  Taeje CHO

IPC: H01L25/10 ,  H01L23/34 ,  H01L21/56 ,  H01L23/367 ,  H01L23/31 ,  H01L25/00 ,  H01L23/373

CPC classification number: H01L25/105 ,  H01L23/3128 ,  H01L23/345 ,  H01L23/36 ,  H01L23/3677 ,  H01L24/19 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/181 ,  H01L2924/00

Abstract: Provided are semiconductor packages and methods of fabricating the same. The method may include mounting a first semiconductor chip including chip and heat-transfer regions and a lower heat-transfer pattern disposed on the heat-transfer region, on a substrate, mounting a second semiconductor chip on the chip region of the first semiconductor chip, forming a mold layer on the substrate to enclose the first and second semiconductor chips, forming an opening in the mold layer to expose at least a portion of the lower heat-transfer pattern, forming a heat-pathway pattern in the opening, and forming a heat-dissipating part on the second semiconductor chip and the mold layer to be connected to the heat-pathway pattern.

Abstract translation: 提供半导体封装及其制造方法。 该方法可以包括在基板上安装包括芯片和传热区域的第一半导体芯片和设置在传热区域上的较低传热图案，将第二半导体芯片安装在第一半导体芯片的芯片区域上， 在所述基板上形成模具层以包围所述第一和第二半导体芯片，在所述模具层中形成开口以露出所述下部传热图案的至少一部分，以在所述开口中形成热通路图案，并且形成 第二半导体芯片上的散热部件和要连接到热通路图案的模具层。

公开(公告)号：US20160148909A1

公开(公告)日：2016-05-26

申请号：US15010438

申请日：2016-01-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsoo CHUNG ,  Jongyeon KIM ,  In-Young LEE ,  Tae-Je CHO

IPC: H01L25/065 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L21/02016 ,  H01L21/486 ,  H01L21/561 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/16 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/03 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00012

Abstract: Provided are semiconductor packages having through electrodes and methods of fabricating the same. The method may include may include forming a wafer-level package including first semiconductor chips stacked on a second semiconductor chip, forming a chip-level package including fourth semiconductor chips stacked on a third semiconductor chip stacking a plurality of the chip-level packages on a back surface of the second semiconductor substrate of the wafer-level package, polishing the first mold layer of the wafer-level package and the first semiconductor chips to expose a first through electrodes of the first semiconductor chip, and forming outer electrodes on the polished first semiconductor chips to be connected to the first through electrodes, respectively.

公开(公告)号：US20150001685A1

公开(公告)日：2015-01-01

申请号：US14264123

申请日：2014-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Hyunsoo CHUNG ,  Jongyeon KIM ,  In-Young LEE ,  Tae-Je CHO

IPC: H01L21/48 ,  H01L21/02 ,  H01L23/538 ,  H01L25/00 ,  H01L25/07

CPC classification number: H01L25/0657 ,  H01L21/02016 ,  H01L21/486 ,  H01L21/561 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/16 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/03 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00012

Abstract: Provided are semiconductor packages having through electrodes and methods of fabricating the same. The method may include may include forming a wafer-level package including first semiconductor chips stacked on a second semiconductor chip, forming a chip-level package including fourth semiconductor chips stacked on a third semiconductor chip stacking a plurality of the chip-level packages on a back surface of the second semiconductor substrate of the wafer-level package, polishing the first mold layer of the wafer-level package and the first semiconductor chips to expose a first through electrodes of the first semiconductor chip, and forming outer electrodes on the polished first semiconductor chips to be connected to the first through electrodes, respectively.

Abstract translation: 提供了具有通孔的半导体封装及其制造方法。 该方法可以包括形成包括层叠在第二半导体芯片上的第一半导体芯片的晶片级封装，形成芯片级封装，芯片级封装包括堆叠在堆叠多个芯片级封装上的第三半导体芯片上的第四半导体芯片 晶片级封装的第二半导体衬底的后表面，抛光晶片级封装的第一模具层和第一半导体芯片，以暴露第一半导体芯片的第一贯穿电极，并在第一半导体芯片上形成外部电极 半导体芯片分别连接到第一贯通电极。

公开(公告)号：US20150130083A1

公开(公告)日：2015-05-14

申请号：US14488707

申请日：2014-09-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Sick PARK ,  In-Young LEE ,  Byoung-Soo KWAK ,  Min-Soo KIM ,  Sang-Wook PARK ,  Tae-Je CHO

IPC: H01L25/065 ,  H01L23/34 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/36 ,  H01L23/481 ,  H01L23/49816 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83191 ,  H01L2224/94 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2924/00

Abstract: A semiconductor device and a method of fabricating the same includes providing a first semiconductor chip which has first connection terminals, providing a second semiconductor chip which comprises top and bottom surfaces facing each other and has second connection terminals and a film-type first underfill material formed on the bottom surface thereof, bonding the first semiconductor chip to a mounting substrate by using the first connection terminals, bonding the first semiconductor chip and the second semiconductor chip by using the first underfill material, and forming a second underfill material which fills a space between the mounting substrate and the first semiconductor chip and covers side surfaces of the first semiconductor chip and at least part of side surfaces of the second semiconductor chip.

Abstract translation: 一种半导体器件及其制造方法包括提供具有第一连接端子的第一半导体芯片，提供第二半导体芯片，该第二半导体芯片包括彼此相对的顶表面和底表面，并且具有第二连接端子和形成的膜型第一底部填充材料 在其底面上，通过使用第一连接端子将第一半导体芯片接合到安装基板，通过使用第一底部填充材料接合第一半导体芯片和第二半导体芯片，以及形成填充第二底部填充材料之间的空间的第二底部填充材料 安装基板和第一半导体芯片，并且覆盖第一半导体芯片的侧表面和第二半导体芯片的至少一部分侧表面。

公开(公告)号：US20140377909A1

公开(公告)日：2014-12-25

申请号：US14264120

申请日：2014-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsoo CHUNG ,  Keum-Hee MA ,  In-Young LEE ,  Moon Gi CHO ,  Chajea JO ,  Taeje CHO

IPC: H01L21/56

CPC classification number: H01L21/561 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/119 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/81005 ,  H01L2224/81007 ,  H01L2224/92 ,  H01L2224/92227 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2224/03 ,  H01L21/568 ,  H01L21/78 ,  H01L2224/1191 ,  H01L2924/00 ,  H01L2224/13099 ,  H01L2924/00012

Abstract: Semiconductor packages having through electrodes and methods for fabricating the same are provided. The method may comprise providing a first substrate including a first circuit layer, forming a front mold layer on a front surface of the first substrate, grinding a back surface of the first substrate, forming a first through electrode that penetrates the first substrate to be electrically connected to the first circuit layer, providing a second substrate on the back surface of the first substrate, the second substrate including a second circuit layer that is electrically connected to the first through electrode, forming a back mold layer on the back surface of the first substrate, the back mold layer encapsulating the second substrate, and removing the front mold layer.

Abstract translation: 提供了具有通过电极的半导体封装及其制造方法。 该方法可以包括提供包括第一电路层的第一衬底，在第一衬底的前表面上形成前模层，研磨第一衬底的后表面，形成穿透第一衬底的第一贯穿电极以电 连接到第一电路层，在第一衬底的背表面上提供第二衬底，第二衬底包括电连接到第一贯通电极的第二电路层，在第一衬底的后表面上形成后模层 衬底，封装第二衬底的后模层，以及去除前模层。