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    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    1.
    发明公开
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开

    公开(公告)号：US20240365535A1

    公开(公告)日：2024-10-31

    申请号：US18397014

    申请日：2023-12-27

    Applicant: SAMSUNG ELECTRONICS CO, LTD.

    Inventor： Jongmin KIM ,  Kiseok LEE ,  Bongsoo KIM ,  Chan-Sic YOON

    IPC: H10B12/00

    CPC classification number: H10B12/488 ,  H10B12/315 ,  H10B12/482 ,  H10B12/485

    Abstract: A semiconductor device includes a first active pattern including a first edge portion and a second edge portion, which are spaced apart from each other in a first direction; a first word line between the first edge portion of the first active pattern and the second edge portion of the first active pattern and extending in a second direction that crosses the first direction; a bit line on the first edge portion of the first active pattern and extending in a third direction that crosses the first direction and the second direction; and a storage node contact on the second edge portion of the first active pattern, wherein a top surface of the first edge portion is at a level higher than a top surface of the second edge portion.

    SEMICONDUCTOR DEVICES
    2.
    发明公开
    SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20240315005A1

    公开(公告)日：2024-09-19

    申请号：US18388266

    申请日：2023-11-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kiseok LEE ,  Sangjae PARK ,  Huijung KIM ,  Taejin PARK ,  Chansic YOON ,  Myeongdong LEE

    IPC: H10B12/00

    CPC classification number: H10B12/315 ,  H10B12/0335 ,  H10B12/482

    Abstract: A semiconductor device includes an active pattern array including active patterns on a substrate; a first contact structure on a central portion of each active pattern; a bit line structure on the first contact structure; a second contact structure on an end of each active pattern; a third contact structure on the second contact structure; and a capacitor electrically connected to the third contact structure, wherein the active pattern array includes active pattern rows spaced apart from each other in a second direction parallel the substrate, the active pattern rows include active patterns spaced apart from each other in a first direction parallel to the substrate, the active patterns extend in a third direction having an acute angle with the first/second directions, the active patterns in the rows are aligned in the first direction, and the second contact structure has a rectangular shape in a plan view.

    SEMICONDUCTOR MEMORY DEVICES
    5.
    发明公开
    SEMICONDUCTOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20230180456A1

    公开(公告)日：2023-06-08

    申请号：US18059492

    申请日：2022-11-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Euichul JEONG ,  Kiseok LEE ,  Wonki ROH ,  Hyungeun CHOI

    IPC: H10B12/00

    CPC classification number: H01L27/10805 ,  H01L27/1085 ,  H01L27/10873 ,  H01L27/10885

    Abstract: A semiconductor memory device including a transistor body extending in a first horizontal direction and including a first source/drain region, a single-crystal channel layer, and a second source/drain region sequentially arranged in the first horizontal direction, a gate electrode layer extending in a second horizontal direction orthogonal to the first horizontal direction and covering upper and lower surfaces of the single-crystal channel layer, a bit line connected to the first source/drain region, extending in a vertical direction, and having a first width in the second horizontal direction, a spacer covering upper and lower surfaces of the first source/drain region and having a second width greater than the first width, and a cell capacitor on a side opposite to the bit line with respect to the transistor body in the first horizontal direction and including lower and upper electrode layers and a capacitor dielectric layer therebetween may be provided.

    SEMICONDUCTOR MEMORY DEVICE
    6.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20230055499A1

    公开(公告)日：2023-02-23

    申请号：US17805706

    申请日：2022-06-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kiseok LEE ,  Keunnam KIM ,  Hui-Jung KIM ,  Wonsok LEE ,  Min Hee CHO

    IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/11573

    Abstract: A semiconductor memory device may be provided. The semiconductor memory device may include a bit line, a channel pattern on the bit line, the channel pattern including a horizontal channel portion, which is provided on the bit line, and a vertical channel portion, which is vertically extended from the horizontal channel portion, a word line provided on the channel pattern to cross the bit line, the word line including a horizontal portion, which is provided on the horizontal channel portion, and a vertical portion, which is vertically extended from the horizontal portion to face the vertical channel portion, and a gate insulating pattern provided between the channel pattern and the word line.

    SEMICONDUCTOR MEMORY DEVICE
    7.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20230044856A1

    公开(公告)日：2023-02-09

    申请号：US17873242

    申请日：2022-07-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Taejin PARK ,  Kiseok LEE ,  Hui-Jung KIM ,  Yoosang HWANG

    IPC: H01L29/423 ,  H01L21/768 ,  H01L21/762 ,  H01L21/02 ,  G11C5/06

    Abstract: A semiconductor memory device including a substrate including an active pattern that includes a first source/drain region and a second source/drain region; an insulating layer on the substrate; a line structure on the insulating layer and extending in a first direction to cross the active pattern, the line structure penetrating the insulating layer on the first source/drain region and including a bit line electrically connected to the first source/drain region; and a contact spaced apart from the line structure and electrically connected to the second source/drain region, wherein the bit line includes a first portion vertically overlapped with the first source/drain region; and a second portion vertically overlapped with the insulating layer, and wherein a lowermost level of a top surface of the first portion of the bit line is at a level lower than a lowermost level of a top surface of the second portion of the bit line.

    SEMICONDUCTOR MEMORY DEVICE
    8.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20220102352A1

    公开(公告)日：2022-03-31

    申请号：US17241860

    申请日：2021-04-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kiseok LEE ,  Kyunghwan LEE ,  Dongoh KIM ,  Yongseok KIM ,  Hui-jung KIM ,  Min Hee CHO

    IPC: H01L27/108

    Abstract: A semiconductor memory device includes a bit line extending in a first direction, a channel pattern on the bit line, the channel pattern including first and second vertical portions facing each other and a horizontal portion connecting the first and second vertical portions, first and second word lines provided on the horizontal portion and between the first and second vertical portions and extended in a second direction crossing the bit line, and a gate insulating pattern provided between the first word line and the channel pattern and between the second word line and the channel pattern.

    SEMICONDUCTOR MEMORY DEVICE
    9.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210408008A1

    公开(公告)日：2021-12-30

    申请号：US17471824

    申请日：2021-09-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kiseok LEE ,  Chan-Sic YOON ,  Augustin HONG ,  Keunnam KIM ,  Dongoh KIM ,  Bong-Soo KIM ,  Jemin PARK ,  Hoin LEE ,  Sungho JANG ,  Kiwook JUNG ,  Yoosang HWANG

    IPC: H01L27/108 ,  H01L27/24

    Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.

    SEMICONDUCTOR MEMORY DEVICES
    10.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 有权

    公开(公告)号：US20210057416A1

    公开(公告)日：2021-02-25

    申请号：US17090419

    申请日：2020-11-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jiyoung KIM ,  Kiseok LEE ,  Bong-Soo KIM ,  Junsoo KIM ,  Dongsoo WOO ,  Kyupil LEE ,  HyeongSun HONG ,  Yoosang HWANG

    IPC: H01L27/108 ,  H01L27/06 ,  H01L49/02

    Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a substrate. The semiconductor memory device includes a plurality of memory cell transistors vertically stacked on the substrate. The semiconductor memory device includes a first conductive line connected to a source region of at least one of the plurality of memory cell transistors. The semiconductor memory device includes a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors. Moreover, the semiconductor memory device includes a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors.

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