Data storage devices and methods for manufacturing the same

    公开(公告)号:US11683989B2

    公开(公告)日:2023-06-20

    申请号:US17169759

    申请日:2021-02-08

    CPC classification number: H10N50/01 H10B61/00 H10N50/10 H10N50/80

    Abstract: A method of manufacturing a data storage device may include forming a magnetic tunnel junction layer on a substrate, irradiating a first ion beam on the magnetic tunnel junction layer to form magnetic tunnel junction patterns separated from each other, irradiating a second ion beam on the magnetic tunnel junction layer, and irradiating a third ion beam on the magnetic tunnel junction layer. The first ion beam may be irradiated at a first incident angle. The second ion beam may be irradiated at a second incident angle that may be smaller than the first incident angle. The third ion beam may be irradiated to form sidewall insulating patterns on sidewalls of the magnetic tunnel junction patterns based on re-depositing materials separated by the third ion beam on the sidewalls of the magnetic tunnel junction patterns.

    Data storage devices and methods for manufacturing the same

    公开(公告)号:US10978638B2

    公开(公告)日:2021-04-13

    申请号:US16837424

    申请日:2020-04-01

    Abstract: A method of manufacturing a data storage device may include forming a magnetic tunnel junction layer on a substrate, irradiating a first ion beam on the magnetic tunnel junction layer to form magnetic tunnel junction patterns separated from each other, irradiating a second ion beam on the magnetic tunnel junction layer, and irradiating a third ion beam on the magnetic tunnel junction layer. The first ion beam may be irradiated at a first incident angle. The second ion beam may be irradiated at a second incident angle that may be smaller than the first incident angle. The third ion beam may be irradiated to form sidewall insulating patterns on sidewalls of the magnetic tunnel junction patterns based on re-depositing materials separated by the third ion beam on the sidewalls of the magnetic tunnel junction patterns.

    Semiconductor devices
    6.
    发明授权

    公开(公告)号:US10395979B2

    公开(公告)日:2019-08-27

    申请号:US16015809

    申请日:2018-06-22

    Abstract: A semiconductor device includes a first lower insulating interlayer, a protection insulating layer, and a first upper insulating interlayer that are sequentially stacked on a substrate, and a conductive pattern penetrating the first upper insulating interlayer, the protection insulating layer; and the first lower insulating interlayer. The conductive pattern includes a line part extending in a direction parallel to an upper surface of the substrate and contact parts extending from the line part toward the substrate. The contact parts are separated from each other with an insulating pattern therebetween. The insulating pattern includes a portion of each of the first upper insulating interlayer, the protection insulating layer, and the first lower insulating interlayer. At least a portion of the insulating pattern has a stepped profile.

    DATA STORAGE DEVICES AND METHODS FOR MANUFACTURING THE SAME

    公开(公告)号:US20180375019A1

    公开(公告)日:2018-12-27

    申请号:US16110483

    申请日:2018-08-23

    Abstract: A method of manufacturing a data storage device may include forming a magnetic tunnel junction layer on a substrate, irradiating a first ion beam on the magnetic tunnel junction layer to form magnetic tunnel junction patterns separated from each other, irradiating a second ion beam on the magnetic tunnel junction layer, and irradiating a third ion beam on the magnetic tunnel junction layer. The first ion beam may be irradiated at a first incident angle. The second ion beam may be irradiated at a second incident angle that may be smaller than the first incident angle. The third ion beam may be irradiated to form sidewall insulating patterns on sidewalls of the magnetic tunnel junction patterns based on re-depositing materials separated by the third ion beam on the sidewalls of the magnetic tunnel junction patterns.

    Method of forming patterns and method of manufacturing a semiconductor device using the same

    公开(公告)号:US09905754B1

    公开(公告)日:2018-02-27

    申请号:US15630046

    申请日:2017-06-22

    CPC classification number: H01L43/12 H01L27/222

    Abstract: In a method of forming a pattern of a semiconductor device, a first mask layer and an anti-reflective coating layer may be sequentially formed on a substrate. A photoresist layer may be formed on the anti-reflective coating layer. The photoresist layer may be exposed and developed to form a first preliminary photoresist pattern. A first ion beam etching process may be performed on the first preliminary photoresist pattern to form a second preliminary photoresist pattern. A second ion beam etching process may be performed on the second preliminary photoresist pattern to form a photoresist pattern. A second incident angle of an ion beam in the second ion beam etching process may be greater than a first incident angle of an ion beam in the first ion beam etching process. The anti-reflective coating layer and the first mask layer may be etched using the photoresist pattern as an etching mask to form a mask structure.

    SEMICONDUCTOR MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME

    公开(公告)号:US20220216402A1

    公开(公告)日:2022-07-07

    申请号:US17468739

    申请日:2021-09-08

    Abstract: A semiconductor memory device in which performance is improved by reducing a wiring resistance is provided. The semiconductor memory device comprising an inter-wiring insulation film on a substrate, a first wiring pattern extending in a first direction, in the inter-wiring insulation film, a barrier insulation film that is on an upper surface of the inter-wiring insulation film, a barrier conductive pattern electrically connected to the first wiring pattern, in the barrier insulation film, a memory cell electrically connected to the barrier conductive pattern and including a selection pattern and a variable resistor pattern, and a second wiring pattern extending in a second direction intersecting the first direction, on the memory cell, wherein a width of the barrier conductive pattern in the second direction is different from a width in the second direction of a portion of the memory cell that is adjacent to the barrier conductive pattern.

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