SUBSTRATE PROCESSING APPARATUS
    1.
    发明公开

    公开(公告)号:US20240145288A1

    公开(公告)日:2024-05-02

    申请号:US18323719

    申请日:2023-05-25

    CPC classification number: H01L21/6833 C23C16/4583

    Abstract: A substrate processing apparatus includes a chamber providing a space where a semiconductor process is performed on a semiconductor substrate, a substrate plate configured to support the semiconductor substrate, the substrate plate having a central region and a peripheral region surrounding the central region, a central embossing pattern on the central region and configured to support a central portion of the semiconductor substrate, a plurality of first embossing patterns radially arranged around the central embossing pattern on the peripheral region, each of the plurality of first embossing patterns extending radially outward from the central embossing pattern with a first length, and a plurality of second embossing patterns respectively provided between the first embossing patterns on the peripheral region, each of the plurality of second embossing patterns extending radially outward from the central embossing pattern with a second length that is less than the first length.

    METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

    公开(公告)号:US20240381616A1

    公开(公告)日:2024-11-14

    申请号:US18636744

    申请日:2024-04-16

    Abstract: A method may include forming a first gate structure on a first region of a substrate, forming a bit line structure on the first gate structure, forming a preliminary contact plug layer including amorphous silicon on the substrate, forming a reflective layer structure on the preliminary contact plug layer, forming a contact plug layer from the preliminary contact plug layer, and forming a capacitor on the contact plug layer. The reflective layer structure may include first and second reflective layers. A refractive index of the second reflective layer may be being greater than that of the first reflective layer. Portions of the second reflective layer may have different thicknesses on first and second regions of the substrate. The forming the contact plug layer may include performing a melting laser annealing (MLA) process on the reflective layer structure to convert the amorphous silicon of the preliminary contact plug layer into polysilicon.

    SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

    公开(公告)号:US20230128492A1

    公开(公告)日:2023-04-27

    申请号:US18049732

    申请日:2022-10-26

    Abstract: There is provided a semiconductor memory device capable of improving the performance and/or the reliability of a device. The semiconductor memory device includes a substrate having a cell area and a peripheral area defined along a periphery of the cell area, wherein the cell area includes an active area defined by a cell element separation film, a cell area separation film in the substrate and defining the cell area, and a plurality of storage contacts connected to the active area, and arranged along a first direction. The plurality of storage contacts includes a first storage contact, a second storage contact, and a third storage contact, wherein the second storage contact is between the first storage contact and the third storage contact, each of the first storage contact and the third storage contact contains or surrounds or defines an airgap, and the second storage contact is free of an airgap.

    METHOD OF FABRICATING A SEMICONDUCTOR DEVICE

    公开(公告)号:US20220199473A1

    公开(公告)日:2022-06-23

    申请号:US17386323

    申请日:2021-07-27

    Abstract: A method of fabricating a semiconductor device is disclosed. The method may include forming a parent pattern, forming an upper thin film on the parent pattern, forming a child pattern on the upper thin film, measuring a diffraction light from the parent and child patterns to obtain an intensity difference curve of the diffraction light versus its wavelength, and performing an overlay measurement process on the parent and child patterns using the diffraction light, which has the same wavelength as a peak of the intensity difference curve located near a peak of reflectance of the parent and child patterns, to obtain an overlay measurement value.

Patent Agency Ranking