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公开(公告)号：US10755776B2
公开(公告)日：2020-08-25
申请号：US16217883
申请日：2018-12-12
Applicant: Seagate Technology LLC
Inventor： Sundararajan Sankaranarayanan , Erich F. Haratsch
Abstract: Techniques are provided for adaptive read threshold voltage tracking with gap estimation between default read threshold voltages. A read threshold voltage for a memory is adjusted by estimating a gap between two adjacent default read threshold voltages using binary data from the memory, wherein the gap is estimated using statistical characteristics of at least one of two adjacent memory levels of the memory; computing an adjusted read threshold voltage associated with the two adjacent memory levels by using the statistical characteristics of the two adjacent memory levels and the gap; and updating the read threshold voltage with the adjusted read threshold voltage. Pages of the memory are optionally read at multiple read threshold offset locations to obtain disparity statistics, which can be used to estimate mean and/or standard deviation values for a given memory level. The gap is optionally estimated using the mean and/or standard deviation values.
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公开(公告)号：US10347343B2
公开(公告)日：2019-07-09
申请号：US14928181
申请日：2015-10-30
Applicant: Seagate Technology LLC
Inventor： Sundararajan Sankaranarayanan , Erich F. Haratsch
Abstract: Methods and apparatus are provided for adaptive read threshold voltage tracking with separate characterization on each side of a voltage distribution about a distribution mean. A read threshold voltage for a memory is adjusted by determining statistical characteristics of two adjacent memory levels based at least in part on a type of statistical distribution of the memory levels and a distribution of data values read from cells using a plurality of read threshold voltages, wherein the statistical characteristics of the two adjacent memory levels are characterized independently on two sides about at least one mean of the statistical distribution; computing an adjusted read threshold voltage associated with the two adjacent memory levels by using the statistical characteristics of the two adjacent memory levels; and updating the read threshold voltage based on the adjusted read threshold voltage. The adjustment is optionally performed responsive to one or more read errors.
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3.发明申请公开(公告)号：US20180329642A1
公开(公告)日：2018-11-15
申请号：US15593439
申请日：2017-05-12
Applicant: Seagate Technology LLC
Inventor： Hongmei Xie , AbdelHakim S. Alhussien , Alex Ga Hing Tang , Sundararajan Sankaranarayanan , Erich F. Haratsch
IPC: G06F3/06
CPC classification number: G06F3/0641 , G06F3/0608 , G06F3/0679 , H03M7/30 , H03M7/3091 , H03M7/6088
Abstract: Data compression techniques are provided that remove redundancy across the boundary of compression search engines. An illustrative method comprises splitting the data frame into a plurality of sub-chunks; comparing at least two of the plurality of sub-chunks to one another to remove at least one sub-chunk from the plurality of sub-chunks that substantially matches at least one other sub-chunk to generate a remaining plurality of sub-chunks; generating matching sub-chunk information for data reconstruction identifying the at least one removed sub-chunk and the corresponding substantially matched at least one other sub-chunk; grouping the remaining plurality of sub-chunks into sub-units; removing substantially repeated patterns within the sub-units to generate corresponding compressed sub-units; and combining the compressed sub-units with the matching sub-chunk information to generate a compressed data frame. The data frame optionally comprises one or more host pages compressed substantially simultaneously, and the compressed data frame for a plurality of host pages compressed substantially simultaneously comprises a host page address for each host page.
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公开(公告)号：US20180287635A1
公开(公告)日：2018-10-04
申请号：US15478895
申请日：2017-04-04
Applicant: Seagate Technology LLC
Inventor： Ivana Djurdjevic , Ara Patapoutian , Zheng Wang , AbdelHakim Alhussien , Sundararajan Sankaranarayanan , Ludovic Danjean , Erich F. Haratsch
IPC: H03M13/11
CPC classification number: H03M13/1111
Abstract: Method and apparatus for decoding data. In some embodiments, an LDPC decoder has a variable node circuit (VNC) with a plurality of variable nodes configured to store bit reliability values of m-bit code bits. A check node circuit (CNC) has a plurality of check nodes configured to perform parity check operations upon n-bit messages from the VNC. Each n-bit message is formed from a combination of the bit reliability values and stored messages from the check nodes. A pre-saturation compensation circuit is configured to maintain a magnitude of each n-bit message received by the CNC below a saturation limit comprising the maximum value that can be expressed using p bits, with p less than n and each of the n-bit messages received by the CNC having a different magnitude. The pre-saturation compensation circuit may apply different scaling and/or bias factors to the n-bit messages over different decoding iterations.
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公开(公告)号：US20180182465A1
公开(公告)日：2018-06-28
申请号：US15850273
申请日：2017-12-21
Applicant: Seagate Technology LLC
Inventor： Abdel Hakim Alhussien , Ludovic Danjean , Sundararajan Sankaranarayanan , Erich Franz Haratsch
Abstract: Apparatus and method for reducing read disturbed data in a non-volatile memory (NVM). Read operations applied to a first location in the NVM are counted to accumulate a read disturb count (RDC) value. Once the RDC value reaches a predetermined threshold, a flag bit is set and a first bit error statistic (BES) value is evaluated. If acceptable, the RDC value is reduced and additional read operations are applied until the RDC value reaches the predetermined threshold a second time. A second BES value is evaluated and data stored at the first location are relocated if an unacceptable number of read errors are detected by the second BES value. Different thresholds are applied to the first and second BES values so that fewer read errors are acceptable during evaluation of the second BES value as compared to the first BES value.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20180011753A1
公开(公告)日：2018-01-11
申请号：US15639019
申请日：2017-06-30
Applicant: Seagate Technology LLC
CPC classification number: G06F11/076 , G06F11/0727 , G06F11/0775 , G06F11/1012 , G11C11/5642 , G11C16/08 , G11C16/26 , G11C16/28 , G11C29/021 , G11C29/028 , G11C29/52 , G11C2029/0409 , G11C2029/0411 , H03M13/1108 , H03M13/1111 , H03M13/3707 , H03M13/3723 , H03M13/612 , H03M13/6325
Abstract: Adaptive read threshold voltage tracking techniques are provided that employ bit error rate estimation based on a non-linear syndrome weight mapping. An exemplary device comprises a controller configured to determine a bit error rate for at least one of a plurality of read threshold voltages in a memory using a non-linear mapping of a syndrome weight to the bit error rate for the at least one of the plurality of read threshold voltages.
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公开(公告)号：US09548128B2
公开(公告)日：2017-01-17
申请号：US14961865
申请日：2015-12-07
Applicant: Seagate Technology LLC
IPC: H03M13/03 , G11C16/28 , H03M13/11 , G11C11/56 , G11C29/02 , G11C16/08 , G11C16/26 , G11C29/42 , G11C29/44
CPC classification number: G11C16/28 , G11C11/5642 , G11C16/08 , G11C16/26 , G11C29/026 , G11C29/028 , G11C29/42 , G11C2029/4402 , H03M13/1117 , H03M13/1125
Abstract: An apparatus for reading a non-volatile memory includes a tracking module operable to calculate means and variances of voltage level distributions in a non-volatile memory and to calculate at least one reference voltage to be used when reading the non-volatile memory based on the means and variances, a likelihood generator operable to calculate at least one other reference voltage to be used when reading the non-volatile memory, wherein the at least one other reference voltage is based at least in part on a predetermined likelihood value constellation, and to map read patterns from the non-volatile memory to likelihood values, and a read controller operable to read the non-volatile memory using the at least one reference voltage and the at least one other reference voltage to yield the read patterns.
Abstract translation: 用于读取非易失性存储器的装置包括跟踪模块，其可操作以计算非易失性存储器中的电压电平分布的平均值和方差，并且计算当基于所述非易失性存储器读取非易失性存储器时要使用的至少一个参考电压 平均值和方差，似然发生器可操作以计算在读取非易失性存储器时要使用的至少一个其它参考电压，其中至少一个其它参考电压至少部分地基于预定似然值星座，并且 将从非易失性存储器读取图案映射到似然值，以及读取控制器，其可操作以使用所述至少一个参考电压和所述至少一个其它参考电压来读取所述非易失性存储器以产生所述读取模式。
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公开(公告)号：US09455004B2
公开(公告)日：2016-09-27
申请号：US14990129
申请日：2016-01-07
Applicant: Seagate Technology LLC
Inventor： AbdelHakim S. Alhussien , Yunxiang Wu , Sundararajan Sankaranarayanan , Zhengang Chen , Erich F. Haratsch
CPC classification number: G11C7/12 , G11C7/14 , G11C11/5642 , G11C13/004 , G11C16/26 , G11C16/28
Abstract: An apparatus having a circuit and a decoder is disclosed. The circuit is configured to adjust an initial one of a plurality of reference voltages in a read channel of a memory by shifting the initial reference voltage an amount toward a center of a window and read a codeword from the memory a number of times. The window bounds a sweep of the reference voltages. Each retry of the reads uses a respective reference voltage from a pattern of the reference voltages. The pattern is symmetrically spaced about the initial reference voltage. The pattern fits in the window. The decoder is configured to generate read data by performing an iterative decoding procedure on the codeword based on the reads.
Abstract translation: 公开了一种具有电路和解码器的装置。 电路被配置为通过将初始参考电压移向窗口中心的量来调整存储器的读通道中的多个参考电压中的初始值，并从存储器读取码字多次。 窗口限制了参考电压的扫描。 读取的每次重试使用来自参考电压的图案的相应参考电压。 该图案围绕初始参考电压对称地间隔开。 图案适合窗户。 解码器被配置为通过基于读取对码字执行迭代解码过程来生成读取数据。
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9.发明授权公开(公告)号：US09165597B2
公开(公告)日：2015-10-20
申请号：US13931274
申请日：2013-06-28
Applicant: Seagate Technology LLC
Inventor： Sundararajan Sankaranarayanan , Raman Venkataramani , Rishi Ahuja
CPC classification number: G11B20/10046 , G11B13/045 , G11B20/10222
Abstract: Apparatus and method for recovering data from a multi-channel input signal, such as but not limited to a readback signal from a bit patterned medium (BPM) having a plurality of subtracks. In accordance with some embodiments, a single input single output (SISO) equalizer is adapted to generate equalized outputs responsive to alternating subchannels of the multi-channel input signal. A detector is adapted to generate estimates of data symbols represented by the input signal responsive to the equalized outputs. A switching circuit is adapted to switch in different equalizer coefficients for use by the SISO equalizer for each of the alternating subchannels in the input signal.
Abstract translation: 用于从多通道输入信号恢复数据的装置和方法，例如但不限于具有多个子轨道的位图形介质（BPM）的回读信号。 根据一些实施例，单输入单输出（SISO）均衡器适于产生响应于多通道输入信号的交替子信道的均衡输出。 检测器适于响应于均衡的输出而产生由输入信号表示的数据符号的估计。 开关电路适于切换不同的均衡器系数，供SISO均衡器用于输入信号中的每个交替子信道。
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10.发明授权公开(公告)号：US10388368B2
公开(公告)日：2019-08-20
申请号：US15799497
申请日：2017-10-31
Applicant: Seagate Technology LLC
Inventor： Ludovic Danjean , Sundararajan Sankaranarayanan , Erich F. Haratsch
Abstract: Adaptive read reference voltage tracking techniques are provided that employ charge leakage mitigation. An exemplary device for use with multi-level memory cells, comprises a controller configured to: after a predefined time interval that approximates a settling time after a programming of the multi-level memory cells until a charge leakage of one or more of the multi-level memory cells has settled, determine a plurality of read reference voltages for the multi-level memory cells using a post-programming adaptive tracking algorithm; and employ the plurality of read reference voltages to read data from the multi-level memory cells. The reference voltage offsets are optionally determined based on a shift in the read reference voltages after the predefined time interval since the programming of the multi-level memory cells.
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