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    Logic gate circuit and parallel bit test circuit for semiconductor memory devices, capable of operation at low power source levels
    1.
    发明授权
    Logic gate circuit and parallel bit test circuit for semiconductor memory devices, capable of operation at low power source levels 失效
    用于半导体存储器件的逻辑门电路和并行位测试电路，能够在低电源电平下工作

    公开(公告)号：US5646897A

    公开(公告)日：1997-07-08

    申请号：US426384

    申请日：1995-04-21

    申请人： Seigou Yukutake ,  Masahiro Iwamura ,  Kinya Mitsumoto ,  Takashi Akioka ,  Noboru Akiyama

    发明人： Seigou Yukutake ,  Masahiro Iwamura ,  Kinya Mitsumoto ,  Takashi Akioka ,  Noboru Akiyama

    IPC分类号： G11C7/10 ,  G11C29/34 ,  G11C29/50 ,  G11C7/00

    CPC分类号： G11C29/028 ,  G11C29/50 ,  G11C7/1051 ,  G11C11/41 ,  G11C2029/5004 ,  G11C29/34

    摘要： A logic circuit is provided for a memory device which can be operated at a high speed with a lower voltage power source level than conventional devices. This logic circuit can be used in a multi-bit test circuit executing the wired-OR-logic operation of complementary logic signals from a plurality of pre-sense amplifiers, receiving the output of the wired-OR-logic operation by an emitter follower using a bipolar transistor, and outputting an AND signal of the complementary logic signals by a level comparing circuit. A sense amplifier is also provided for executing the wired-OR-logic operation of complementary logic signals from a plurality of pre-sense amplifiers, raising the level of the output of the wired-OR-logic operation by a level shift circuit having a semiconductor element for applying an inverse bias potential to an input signal, executing the wired-OR-operation of the shifted up output and outputs from other blocks, and receiving and amplifying the output of the wired-OR-logic operation.

    摘要翻译： 提供了一种用于存储器件的逻辑电路，其可以以比传统器件更低的电压电源电平在高速下操作。 该逻辑电路可以用于执行来自多个预读取放大器的互补逻辑信号的有线或逻辑运算的多位测试电路，通过射极跟随器接收有线或逻辑运算的输出，使用 双极晶体管，并通过电平比较电路输出互补逻辑信号的“与”信号。 还提供读出放大器，用于执行来自多个预读放大器的互补逻辑信号的有线或逻辑运算，通过具有半导体的电平移位电路提高布线或逻辑运算的输出电平 元件，用于对输入信号施加反向偏置电位，执行移位上升输出的线或运算和其他块的输出，以及接收和放大有线逻辑运算的输出。

    Semiconductor device capable of holding signals independent of the pulse width of an external clock and a computer system including the semiconductor device
    2.
    发明授权
    Semiconductor device capable of holding signals independent of the pulse width of an external clock and a computer system including the semiconductor device 失效
    能够保持独立于外部时钟的脉冲宽度的信号的半导体器件和包括半导体器件的计算机系统

    公开(公告)号：US5920510A

    公开(公告)日：1999-07-06

    申请号：US934202

    申请日：1997-09-19

    申请人： Seigou Yukutake ,  Takashi Akioka ,  Kinya Mitsumoto ,  Takahiro Nagano ,  Hideo Maejima

    发明人： Seigou Yukutake ,  Takashi Akioka ,  Kinya Mitsumoto ,  Takahiro Nagano ,  Hideo Maejima

    IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C8/06 ,  G11C16/04

    CPC分类号： G11C7/1072 ,  G11C7/22 ,  G11C8/06

    摘要： A semiconductor device and a computer system, incorporating the same, is capable of capturing an external signal at a high speed and stably operating independent of the duty ratio of a clock signal. An external signal ADD is captured into an address latch 22 by a level latch. The level latch is controlled to a through state at the timing in which the external signal is decided and controlled to a latched state in the decision period of the external signal. A pulse generation circuit controls the timing for switching a latch to the through state to a desired timing by a pulse generation circuit 30 in a chip. According to the above structure, the capture of the external signal ADD can be accelerated because the capture of the signal is determined by the setup timing. Moreover, because a latching period is controlled by the pulse generation circuit in the chip, operations are performed in a stable manner without having to depend upon the pulse width of an external clock CLK.

    摘要翻译： 包含该半导体器件和计算机系统的半导体器件和计算机系统能够以与时钟信号的占空比无关地稳定地高速捕获外部信号。 外部信号ADD被电平锁存器捕获到地址锁存器22中。 电平锁存器在外部信号判定时刻的定时被控制为通过状态，并且在外部信号的判定周期中被控制为锁存状态。 脉冲发生电路通过芯片中的脉冲发生电路30控制将锁存器切换到通过状态到期望定时的定时。 根据上述结构，可以加速外部信号ADD的捕获，因为信号的捕获由设置时序确定。 此外，由于锁存周期由芯片中的脉冲发生电路控制，所以以稳定的方式执行操作，而不必依赖于外部时钟CLK的脉冲宽度。

    Isolated bidirectional DC-DC converter
    9.
    发明授权
    Isolated bidirectional DC-DC converter 有权
    隔离双向DC-DC转换器

    公开(公告)号：US07638904B2

    公开(公告)日：2009-12-29

    申请号：US11206226

    申请日：2005-08-18

    申请人： Hiroyuki Shoji ,  Akihiko Kanouda ,  Ryuichi Saito ,  Seigou Yukutake ,  Katsuhiro Higuchi

    发明人： Hiroyuki Shoji ,  Akihiko Kanouda ,  Ryuichi Saito ,  Seigou Yukutake ,  Katsuhiro Higuchi

    IPC分类号： G01R1/20

    CPC分类号： H02M1/34 ,  H02M3/33584 ,  H02M2001/342 ,  Y02B70/1491

    摘要： The DC-DC converter connects a first and a second switching circuit for converting power mutually between direct current and alternating current respectively to a first DC power source and a second DC power source and has a transformer between the AC terminals thereof. Here, between the AC terminals of the second switching circuit and the negative pole terminal of the DC power source, a voltage clamp circuit composed of a series unit of switching devices with a reverse parallel diode and a clamp condenser is connected.An isolated bidirectional DC-DC converter which prevents a reduction in a circulating current at time of buck and an occurrence of a surge voltage at time of voltage boost and realizes highly efficiency, low noise, and miniaturization is provided.

    摘要翻译： DC-DC转换器将用于将直流和交流之间的功率相互转换的第一和第二开关电路分别连接到第一直流电源和第二直流电源，并且在其AC端子之间具有变压器。 这里，在第二开关电路的交流端子和直流电源的负极端子之间，连接由串联的具有反向并联二极管的开关器件和钳位电容器组成的电压钳位电路。 提供一种隔离的双向DC-DC转换器，其防止降压时的循环电流的降低和在升压时的浪涌电压的发生，并且实现高效率，低噪声和小型化。

    SRAM having load transistor formed above driver transistor
    10.
    发明授权
    SRAM having load transistor formed above driver transistor 失效
    具有形成在驱动晶体管上方的负载晶体管的SRAM

    公开(公告)号：US5834851A

    公开(公告)日：1998-11-10

    申请号：US460641

    申请日：1995-06-02

    申请人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

    发明人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

    IPC分类号： H01L27/11

    CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

    摘要： Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially. The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.The source line is formed of a conductive layer identical to that of the word line. The individual data lines of the complementary data line are formed of an identical conductive layer which is different from that of the word line and the source line. The identical conductive layer between the word line and source line and the complementary data line is formed with two word lines: a main word line extended in the first direction identical to that of the word line and source line and used by adopting the divided word line system: and a sub-word line used by adopting the double word line system.

    摘要翻译： 这里公开了一种半导体集成电路器件，其包括具有其存储单元的SRAM，SRAM由通过字线控制的转移MISFET和驱动MISFET构成。 驱动MISFET的栅电极和存储单元的转移MISFET的栅电极和字线分别由不同的导电层形成。 驱动MISFET和转移MISFET分别布置成在栅极长度方向上彼此交叉。 字线在驱动MISFET的栅电极的栅极长度方向上延伸，并且部分地与驱动MISFET的栅电极交叉。 存储器单元的两个转移MISFET的各自的栅极电极与彼此间隔开并沿相同方向延伸的两个相应字线连接。 由两个字线限定的区域配置有两个驱动MISFET和源极线。 源极线由与字线的导电层相同的导电层形成。 互补数据线的各个数据线由与字线和源极线不同的导电层形成。 字线和源极线与互补数据线之间的相同的导电层由两条字线形成：主字线在第一方向上延伸，与字线和源极线相同，并通过采用分割字线 系统：采用双字线系统使用的子字线。