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    SEMICONDUCTOR DEVICE AND DYNAMIC LOGIC CIRCUIT
    1.
    发明申请
    SEMICONDUCTOR DEVICE AND DYNAMIC LOGIC CIRCUIT 有权

    公开(公告)号：US20250166694A1

    公开(公告)日：2025-05-22

    申请号：US19029083

    申请日：2025-01-17

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Tomoaki ATSUMI ,  Kiyoshi KATO ,  Shuhei MAEDA

    IPC: G11C11/4094 ,  H10B12/00 ,  H10D30/67

    Abstract: A semiconductor device whose operating speed is increased is provided. The semiconductor device includes a write word line, a read word line, a write bit line, a read bit line, a first wiring, and a memory cell. The memory cell includes three transistors of a single conductivity type and a capacitor. Gates of the three transistors are electrically connected to the write word line, a first terminal of the capacitor, and the read word line, respectively. A second terminal of the capacitor is electrically connected to the read bit line. A source and a drain of one transistor are electrically connected to the write bit line and the gate of another transistor, respectively. Two of the three transistors are electrically connected in series between the read bit line and the first wiring. A channel formation region of each of the three transistors includes, for example, a metal oxide layer.

    MEMORY DEVICE HAVING ERROR DETECTION FUNCTION, SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE
    2.
    发明申请
    MEMORY DEVICE HAVING ERROR DETECTION FUNCTION, SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE 有权

    公开(公告)号：US20250142803A1

    公开(公告)日：2025-05-01

    申请号：US19006634

    申请日：2024-12-31

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Hitoshi KUNITAKE ,  Tatsuya ONUKI ,  Tomoaki ATSUMI ,  Kiyoshi KATO

    IPC: H10B12/00 ,  G11C29/52 ,  H10D30/67

    Abstract: A memory device having an error detection function and being capable of storing a large amount of data per unit area is provided. A driver circuit of the memory device is formed using a transistor formed on a semiconductor substrate, and a memory cell of the memory device is formed using a thin film transistor. A plurality of layers each of which includes a memory cell using the thin film transistor can be stacked over the semiconductor substrate, so that the amount of data that can be stored per unit area can be increased. Part of a peripheral circuit including the memory device can be formed using a thin film transistor, and thus, an error detection circuit is formed using the thin film transistor and stacked over the semiconductor substrate.

    STORAGE DEVICE
    3.
    发明申请
    STORAGE DEVICE 有权

    公开(公告)号：US20250107062A1

    公开(公告)日：2025-03-27

    申请号：US18832672

    申请日：2023-01-23

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shunpei YAMAZAKI ,  Tatsuya ONUKI ,  Kiyoshi KATO ,  Hitoshi KUNITAKE ,  Ryota HODO

    IPC: H10B12/00 ,  G11C11/405 ,  G11C11/408

    Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first insulator, a second insulator over the first insulator, and a memory cell including a transistor and a capacitor. The transistor includes an oxide over the first insulator, a first conductor and a second conductor over the oxide, a third insulator over the oxide, and a third conductor over the third insulator. The third insulator and the third conductor are located in a first opening of the second insulator. The capacitor includes a fourth conductor in contact with a top surface of the second conductor, a fourth insulator over the fourth conductor, and a fifth conductor over the fourth insulator. The fourth conductor, the fourth insulator, and the fifth conductor are located in a second opening of the second insulator. A third opening is formed in the first insulator, the second insulator, and the first conductor. A sixth conductor is located in the third opening. The sixth conductor includes a region in contact with part of a top surface of the first conductor and part of a side surface of the first conductor in each of a plurality of layers.

    SEMICONDUCTOR DEVICE, STORAGE DEVICE, AND ELECTRONIC DEVICE
    4.
    发明申请
    SEMICONDUCTOR DEVICE, STORAGE DEVICE, AND ELECTRONIC DEVICE 有权

    公开(公告)号：US20240423096A1

    公开(公告)日：2024-12-19

    申请号：US18691163

    申请日：2022-09-08

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Takanori MATSUZAKI ,  Tatsuya ONUKI ,  Kiyoshi KATO

    IPC: H10N50/10 ,  G11C11/16 ,  H10B61/00 ,  H10N50/85 ,  H10N52/85

    Abstract: A semiconductor device with high storage capacity and low power consumption is provided. The semiconductor device includes first to third conductors, first and second transistors, and an MTJ element. The MTJ element includes a free layer and a fixed layer. In the semiconductor device, the first conductor, the second conductor, the free layer, the fixed layer, the first and second transistors, and the third conductor are provided in this order from the bottom. In particular, in a plan view, the third conductor is positioned in a region overlapping with the first conductor. The first conductor is electrically connected to the second conductor, and the second conductor is electrically connected to the free layer and a first terminal of the first transistor. The fixed layer is electrically connected to a first terminal of the second transistor, and a second terminal of the first transistor is electrically connected to a second terminal of the second transistor and the third conductor. The first transistor and the second transistor each include a metal oxide in a channel formation region.

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