公开(公告)号：US20240371985A1

公开(公告)日：2024-11-07

申请号：US18776570

申请日：2024-07-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hidekazu MIYAIRI ,  Kengo AKIMOTO ,  Kojiro SHIRAISHI

IPC: H01L29/66 ,  H01L21/46 ,  H01L27/12 ,  H01L29/786

Abstract: It is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for manufacturing the semiconductor device with high productivity. In an inverted staggered (bottom gate) thin film transistor, an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, and a buffer layer formed using a metal oxide layer is provided between the semiconductor layer and a source and drain electrode layers. The metal oxide layer is intentionally provided as the buffer layer between the semiconductor layer and the source and drain electrode layers, whereby ohmic contact is obtained.

公开(公告)号：US20240314999A1

公开(公告)日：2024-09-19

申请号：US18596907

申请日：2024-03-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hidekazu MIYAIRI ,  Motoki NAKASHIMA

IPC: H10B12/00

CPC classification number: H10B12/00

Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first transistor, a capacitor, and a second transistor stacked in this order. The first and second transistors each include a semiconductor layer, a first conductor over the semiconductor layer, a first insulator, and a second conductor over the first insulator. In each of the first and second transistors, a side surface of the semiconductor layer is aligned with a side surface of the first conductor; the semiconductor layer and the first conductor each have an opening; the first insulator is inside the opening; the first insulator has a depressed portion reflecting the shape of the opening; and a second conductor fills the depressed portion. The second conductor of the first transistor, one of a pair of electrodes of the capacitor, and the semiconductor layer of the second transistor are connected to each other.

公开(公告)号：US20180190677A1

公开(公告)日：2018-07-05

申请号：US15897318

申请日：2018-02-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsuo ISOBE ,  Shunpei YAMAZAKI ,  Koji DAIRIKI ,  Hiroshi SHIBATA ,  Chiho KOKUBO ,  Tatsuya ARAO ,  Masahiko HAYAKAWA ,  Hidekazu MIYAIRI ,  Akihisa SHIMOMURA ,  Koichiro TANAKA ,  Mai AKIBA

IPC: H01L27/12 ,  B23K26/073 ,  H01L21/02 ,  H01L21/20 ,  H01L21/3213 ,  H01L21/84 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/1222 ,  B23K26/0738 ,  H01L21/02354 ,  H01L21/02356 ,  H01L21/02675 ,  H01L21/02683 ,  H01L21/02686 ,  H01L21/02691 ,  H01L21/2026 ,  H01L21/32139 ,  H01L21/84 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/1274 ,  H01L27/1281 ,  H01L27/1296 ,  H01L29/66757 ,  H01L29/78603 ,  H01L29/78675 ,  H01L29/78696 ,  Y10S118/90 ,  Y10T117/10 ,  Y10T117/1004 ,  Y10T117/1008

Abstract: A semiconductor device production system using a laser crystallization method is provided which can avoid forming grain boundaries in a channel formulation region of a TFT, thereby preventing grain boundaries from lowering the mobility of the TFT greatly, from lowering ON current, and from increasing OFF current. Rectangular or stripe pattern depression and projection portions are formed on an insulating film. A semiconductor film is formed on the insulating film. The semiconductor film is irradiated with continuous wave laser light by running the laser light along the stripe pattern depression and projection portions of the insulating film or along the major or minor axis direction of the rectangle. Although continuous wave laser light is most preferred among laser light, it is also possible to use pulse oscillation laser light in irradiating the semiconductor film.

公开(公告)号：US20170162687A1

公开(公告)日：2017-06-08

申请号：US15432961

申请日：2017-02-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hidekazu MIYAIRI ,  Kazuya HANAOKA ,  Suguru HONDO ,  Shunpei YAMAZAKI

IPC: H01L29/78 ,  H01L29/24 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/66969 ,  H01L29/7854 ,  H01L29/78621 ,  H01L29/7869 ,  H01L29/78696 ,  H01L2029/42388

Abstract: A semiconductor device that operates at high speed. A semiconductor device with favorable switching characteristics. A highly integrated semiconductor device. A miniaturized semiconductor device. The semiconductor device is formed by: fainting a semiconductor film including an opening, on an insulating surface; forming a conductive film over the semiconductor film and in the opening, and removing the conductive film over the semiconductor film to form a conductive pillar in the opening; forming an island-shaped mask over the conductive pillar and the semiconductor film; etching the conductive pillar and the semiconductor film using the mask to form a first electrode and a first semiconductor; forming a gate insulating film on a top surface and a side surface of the first semiconductor; and forming a gate electrode that is in contact with a top surface of the gate insulating film and faces the top surface and the side surface of the first semiconductor.

公开(公告)号：US20170133409A1

公开(公告)日：2017-05-11

申请号：US15410028

申请日：2017-01-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hidekazu MIYAIRI ,  Takeshi OSADA ,  Shunpei YAMAZAKI

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/49

CPC classification number: H01L27/1225 ,  G02F1/1362 ,  H01L27/124 ,  H01L27/1251 ,  H01L27/1255 ,  H01L27/3262 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78606 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/7869

Abstract: As a display device has higher definition, the number of pixels is increased and thus, the number of gate lines and signal lines is increased. When the number of gate lines and signal lines is increased, it is difficult to mount IC chips including driver circuits for driving the gate lines and the signal lines by bonding or the like, whereby manufacturing cost is increased. A pixel portion and a driver circuit for driving the pixel portion are provided on the same substrate, and at least part of the driver circuit comprises a thin film transistor including an oxide semiconductor sandwiched between gate electrodes. A channel protective layer is provided between the oxide semiconductor and a gate electrode provided over the oxide semiconductor. The pixel portion and the driver circuit are provided on the same substrate, which leads to reduction of manufacturing cost.

公开(公告)号：US20160087107A1

公开(公告)日：2016-03-24

申请号：US14954155

申请日：2015-11-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Yutaka OKAZAKI ,  Hidekazu MIYAIRI

IPC: H01L29/786

CPC classification number: H01L29/78606 ,  H01L21/8221 ,  H01L27/0688 ,  H01L29/42384 ,  H01L29/78603 ,  H01L29/7869 ,  H01L29/78696

Abstract: A structure is employed in which a first protective insulating layer; an oxide semiconductor layer over the first protective insulating layer; a source electrode and a drain electrode that are electrically connected to the oxide semiconductor layer; a gate insulating layer that is over the source electrode and the drain electrode and overlaps with the oxide semiconductor layer; a gate electrode that overlaps with the oxide semiconductor layer with the gate insulating layer provided therebetween; and a second protective insulating layer that covers the source electrode, the drain electrode, and the gate electrode are included. Furthermore, the first protective insulating layer and the second protective insulating layer each include an aluminum oxide film that includes an oxygen-excess region, and are in contact with each other in a region where the source electrode, the drain electrode, and the gate electrode are not provided.

Abstract translation: 采用其中第一保护绝缘层的结构; 在所述第一保护绝缘层上的氧化物半导体层; 与氧化物半导体层电连接的源电极和漏电极; 栅极绝缘层，位于源电极和漏电极之上并与氧化物半导体层重叠; 与所述氧化物半导体层重叠的栅电极，其间设置有所述栅极绝缘层; 并且包括覆盖源电极，漏电极和栅电极的第二保护绝缘层。 此外，第一保护绝缘层和第二保护绝缘层各自包括氧化物膜，该氧化铝膜包括氧过剩区域，并且在源电极，漏电极和栅电极的区域中彼此接触 没有提供

公开(公告)号：US20150349099A1

公开(公告)日：2015-12-03

申请号：US14820008

申请日：2015-08-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hidekazu MIYAIRI ,  Kengo AKIMOTO ,  Kojiro SHIRAISHI

IPC: H01L29/66 ,  H01L29/786 ,  H01L21/46

CPC classification number: H01L29/66969 ,  H01L21/46 ,  H01L27/1225 ,  H01L29/7869

Abstract: It is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for manufacturing the semiconductor device with high productivity. In an inverted staggered (bottom gate) thin film transistor, an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, and a buffer layer formed using a metal oxide layer is provided between the semiconductor layer and a source and drain electrode layers. The metal oxide layer is intentionally provided as the buffer layer between the semiconductor layer and the source and drain electrode layers, whereby ohmic contact is obtained.

Abstract translation: 本发明的目的是提供一种包括具有良好的电性能和高可靠性的薄膜晶体管的半导体器件，以及一种以高生产率制造半导体器件的方法。 在倒置交错（底栅极）薄膜晶体管中，使用含有In，Ga和Zn的氧化物半导体膜作为半导体层，并且在半导体层和源之间设置使用金属氧化物层形成的缓冲层， 漏电极层。 有意地提供金属氧化物层作为半导体层与源极和漏极电极层之间的缓冲层，从而获得欧姆接触。

公开(公告)号：US20150076495A1

公开(公告)日：2015-03-19

申请号：US14484408

申请日：2014-09-12

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hidekazu MIYAIRI

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L21/02565 ,  H01L21/02667 ,  H01L29/66969 ,  H01L29/78642

Abstract: To provide a transistor having highly stable electric characteristics and also a miniaturized structure. Further, also high performance and high reliability of a semiconductor device including the transistor can be achieved. The transistor is a vertical transistor in which a first electrode having an opening, an oxide semiconductor layer, and a second electrode are stacked in this order, a gate insulating layer is provided in contact with side surfaces of the first electrode, the oxide semiconductor layer, and the second electrode, and a ring-shaped gate electrode facing the side surfaces of the first electrode, the oxide semiconductor layer, and the second electrode with the gate insulating layer interposed therebetween is provided. In the opening in the first electrode, an insulating layer in contact with the oxide semiconductor layer is embedded.

Abstract translation: 提供一种具有高度稳定的电特性并且还具有小型化结构的晶体管。 此外，可以实现包括晶体管的半导体器件的高性能和高可靠性。 晶体管是垂直晶体管，其中具有开口的第一电极，氧化物半导体层和第二电极以此顺序堆叠，栅极绝缘层设置成与第一电极的侧表面接触，氧化物半导体层 和第二电极，并且提供了面对第一电极，氧化物半导体层和第二电极的侧表面的环形栅极电极，其间具有栅极绝缘层。 在第一电极的开口中嵌入与氧化物半导体层接触的绝缘层。

公开(公告)号：US20130140557A1

公开(公告)日：2013-06-06

申请号：US13727056

申请日：2012-12-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hidekazu MIYAIRI ,  Kengo AKIMOTO ,  Yasuo NAKAMURA

IPC: H01L29/26

CPC classification number: H01L29/78696 ,  H01L21/02323 ,  H01L21/02565 ,  H01L21/32139 ,  H01L21/465 ,  H01L21/467 ,  H01L21/4763 ,  H01L21/47635 ,  H01L27/1225 ,  H01L29/0692 ,  H01L29/1033 ,  H01L29/24 ,  H01L29/263 ,  H01L29/42364 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78633 ,  H01L29/7869 ,  H01L29/78693

Abstract: To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed.

公开(公告)号：US20130101754A1

公开(公告)日：2013-04-25

申请号：US13656059

申请日：2012-10-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Akihisa Shimomura ,  Hidekazu MIYAIRI

IPC: B23K26/08 ,  B05D3/06

CPC classification number: B23K26/0736 ,  B23K26/0608 ,  B23K26/0738 ,  C03C27/06 ,  H01L51/5246

Abstract: Provided are a method of heating a composition which is applicable to a substrate provided with a material having low heat resistance and a method of forming a glass pattern which leads to reduction of cracks. A composition formed over a substrate is irradiated with a laser beam to bake the paste through local heating. Scan with the laser beam is, performed so that there can be no difference in the laser beam irradiation period between the middle portion and the perimeter portion of the composition. Specifically, irradiation with the laser beam is performed so that the width of the beam spot overlapping with the composition in the scanning direction is substantially uniform.

Abstract translation: 本发明提供一种加热组合物的方法，该组合物适用于具有低耐热性的材料的基材和形成导致裂纹减少的玻璃图案的方法。 用激光束照射在基板上形成的组合物，以通过局部加热来烘烤浆料。 执行用激光束进行扫描，使得组合物的中间部分和周边部分之间的激光束照射周期无差别。 具体地，进行激光束的照射，使得与扫描方向的组成重叠的束斑的宽度大致均匀。