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18 条记录 (耗时 0.028 秒)

    BOARD ON CHIP PACKAGE SUBSTRATE AND MANUFACTURING METHOD THEREOF
    4.
    发明申请
    BOARD ON CHIP PACKAGE SUBSTRATE AND MANUFACTURING METHOD THEREOF 审中-公开
    芯片包装基板及其制造方法

    公开(公告)号：US20110101510A1

    公开(公告)日：2011-05-05

    申请号：US12912202

    申请日：2010-10-26

    申请人： Kyung-Ro YOON ,  Young-Mi Lee ,  Young-Hwan Shin

    发明人： Kyung-Ro YOON ,  Young-Mi Lee ,  Young-Hwan Shin

    IPC分类号： H01L23/495 ,  H01L21/58

    CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L23/49816 ,  H01L24/16 ,  H01L2924/01079 ,  H01L2924/15311

    摘要： A single-layer board on chip package substrate and a manufacturing method thereof are disclosed. In accordance with an embodiment of the present invention, the substrate includes an insulator, a first pad and a second pad, which are provided on an upper surface of the insulator, a through-hole, which is formed in the insulator such that a lower surface of the first pad is exposed, and a solder resist layer, which is formed on the upper surface of the insulator such that at least a portion of the second pad is exposed.

    摘要翻译： 公开了一种单层片上封装衬底及其制造方法。 根据本发明的实施例，基板包括设置在绝缘体的上表面上的绝缘体，第一焊盘和第二焊盘，形成在绝缘体中的通孔使得下部 暴露第一焊盘的表面和形成在绝缘体的上表面上的阻焊层，使得第二焊盘的至少一部分露出。

    Ion implantation mask forming method
    5.
    发明授权
    Ion implantation mask forming method 有权
    离子注入掩模成型方法

    公开(公告)号：US08241512B2

    公开(公告)日：2012-08-14

    申请号：US12289637

    申请日：2008-10-31

    申请人： Yong-Woo Lee ,  Young-Mi Lee ,  Min-Chul Chae ,  Dae-Joung Kim ,  Jae-Seung Hwang

    发明人： Yong-Woo Lee ,  Young-Mi Lee ,  Min-Chul Chae ,  Dae-Joung Kim ,  Jae-Seung Hwang

    IPC分类号： B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00

    CPC分类号： H01L21/3146 ,  H01L21/265 ,  H01L21/3143 ,  H01L21/31608 ,  H01L21/3185

    摘要： A method of forming an ion implantation mask includes forming a field area on a semiconductor substrate, forming an amorphous carbon layer on the semiconductor substrate, forming a hard mask layer on the amorphous carbon layer, forming an etching mask pattern on the hard mask layer, and etching the hard mask layer and the amorphous carbon layer to expose the field area through the etching mask pattern, wherein etching the hard mask layer and the amorphous carbon layer forms a hard mask layer pattern and an amorphous carbon layer pattern.

    摘要翻译： 形成离子注入掩模的方法包括在半导体衬底上形成场区，在半导体衬底上形成非晶碳层，在非晶碳层上形成硬掩模层，在硬掩模层上形成蚀刻掩模图案， 蚀刻硬掩模层和非晶碳层，通过蚀刻掩模图案露出场区，蚀刻硬掩模层和无定形碳层形成硬掩模层图案和无定形碳层图案。

    Method of manufacturing mask
    6.
    发明授权
    Method of manufacturing mask 失效
    制作面膜的方法

    公开(公告)号：US07539970B2

    公开(公告)日：2009-05-26

    申请号：US11590244

    申请日：2006-10-31

    申请人： Sung-Gon Jung ,  Gi-Sung Yeo ,  Young-Mi Lee ,  Han-Ku Cho

    发明人： Sung-Gon Jung ,  Gi-Sung Yeo ,  Young-Mi Lee ,  Han-Ku Cho

    IPC分类号： G06F17/50 ,  G06F19/00 ,  G03F1/00 ,  G21K5/00

    CPC分类号： G03F1/70 ,  G03F1/36

    摘要： A method of manufacturing a mask includes designing a second mask data pattern for forming a first mask data pattern, creating a first emulation pattern, which is determined from the second mask data pattern, using a first emulation, creating a second emulation pattern, which is determined from the first emulation pattern, using a second emulation, comparing a pattern, in which the first and second emulation patterns overlap, with the first mask data pattern, and manufacturing a mask layer, which corresponds to the second mask data pattern, according to results of the comparison.

    摘要翻译： 制造掩模的方法包括设计用于形成第一掩模数据图案的第二掩模数据图案，使用第一仿真创建从第二掩模数据图案确定的第一仿真图案，创建第二仿真图案，其是第二仿真模式 根据第一仿真模式确定，使用第二仿真，将第一和第二仿真模式重叠的模式与第一掩模数据模式进行比较，并根据第二掩模数据模式制造对应于第二掩模数据模式的掩模层 比较结果。

    Thin layer structure and method of forming the same
    8.
    发明授权
    Thin layer structure and method of forming the same 失效
    薄层结构及其形成方法

    公开(公告)号：US07534704B2

    公开(公告)日：2009-05-19

    申请号：US11449839

    申请日：2006-06-09

    申请人： Jae-Kyu Ha ,  Jun Seo ,  Min-Chul Chae ,  Yong-Sun Ko ,  Young-Mi Lee ,  Jae-Seung Hwang

    发明人： Jae-Kyu Ha ,  Jun Seo ,  Min-Chul Chae ,  Yong-Sun Ko ,  Young-Mi Lee ,  Jae-Seung Hwang

    IPC分类号： H01L21/20

    CPC分类号： H01L21/84 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/02667 ,  H01L21/76262 ,  H01L27/1203

    摘要： In a thin layer structure and a method of forming the same, a first preliminary insulation pattern is formed on a substrate and includes a first opening exposing the substrate. One or more preliminary seed patterns including single crystalline silicon are formed in the first opening. A second insulation layer is formed on the first preliminary insulation pattern and the one or more preliminary seed patterns. A second insulation pattern, a first insulation pattern and one or more seed patterns are formed by etching the first and second insulation layers and the one or more preliminary seed patterns. The second insulation pattern includes a second opening having a flat bottom portion. A single crystalline silicon pattern is formed in the second opening, wherein a central thickness of the single crystalline silicon pattern is substantially identical to a peripheral thickness thereof, thereby reducing or preventing a thinning defect in a semiconductor device.

    摘要翻译： 在薄层结构及其形成方法中，在基板上形成第一预备绝缘图案，并且包括暴露基板的第一开口。 在第一开口中形成包括单晶硅的一种或多种初步种子图案。 在第一预备绝缘图案和一个或多个初步种子图案上形成第二绝缘层。 通过蚀刻第一和第二绝缘层和一个或多个初步种子图案来形成第二绝缘图案，第一绝缘图案和一个或多个种子图案。 第二绝缘图案包括具有平坦底部的第二开口。 在第二开口中形成单晶硅图案，其中单晶硅图案的中心厚度与其周边厚度基本相同，从而减少或防止半导体器件中的变薄缺陷。

    Printed circuit board
    9.
    发明申请
    Printed circuit board 审中-公开
    印刷电路板

    公开(公告)号：US20090097220A1

    公开(公告)日：2009-04-16

    申请号：US12010749

    申请日：2008-01-29

    申请人： Young-Mi Lee ,  Suk-Chang Hong ,  Yong-Bin Lee ,  Chin-Kwan Kim

    发明人： Young-Mi Lee ,  Suk-Chang Hong ,  Yong-Bin Lee ,  Chin-Kwan Kim

    IPC分类号： H05K1/02

    CPC分类号： H05K3/3452 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2224/05552 ,  H01L2224/05567 ,  H05K2201/0989 ,  H05K2201/09909 ,  H05K2201/10734 ,  H05K2203/041 ,  H01L2924/00012

    摘要： A printed circuit board is disclosed. The printed circuit board, which has at least one pad on which a solder ball is to be placed, includes a solder resist that covers a surface of the printed circuit board, an opening part that exposes the pad and supports the solder ball, and an extended portion formed in a perimeter of the opening part that allows an underfill to flow in between the printed circuit board and the solder ball. With this printed circuit board, the underfill can be filled in more readily between the printed circuit board and the solder balls, when mounting a component on the printed circuit board.

    摘要翻译： 公开了印刷电路板。 具有至少一个其上要放置焊球的焊盘的印刷电路板包括覆盖印刷电路板的表面的阻焊剂，露出焊盘并支撑焊球的开口部分，以及 延伸部分形成在开口部分的周边，允许底部填充物在印刷电路板和焊球之间流动。 使用该印刷电路板，当将部件安装在印刷电路板上时，底部填充物可以更容易地填充在印刷电路板和焊球之间。

    Methods of fabricating semiconductor device including fin-fet
    10.
    发明授权
    Methods of fabricating semiconductor device including fin-fet 失效
    制造半导体器件的方法包括鳍片

    公开(公告)号：US07745290B2

    公开(公告)日：2010-06-29

    申请号：US11773372

    申请日：2007-07-03

    申请人： Jun Seo ,  Jong-Heui Song ,  Jae-Seung Hwang ,  Min-Chul Chae ,  Woo-Jin Cho ,  Yun-Seung Kang ,  Young-Mi Lee

    发明人： Jun Seo ,  Jong-Heui Song ,  Jae-Seung Hwang ,  Min-Chul Chae ,  Woo-Jin Cho ,  Yun-Seung Kang ,  Young-Mi Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66795 ,  H01L29/7851

    摘要： A method of fabricating a semiconductor device including a fin field effect transistor (Fin-FET) includes forming sacrificial bars on a semiconductor substrate, patterning the sacrificial bars to form sacrificial islands on the semiconductor substrate, forming a device isolation layer to fill a space between the sacrificial islands, selectively removing the sacrificial islands to expose the semiconductor substrate below the sacrificial islands, and anisotropically etching the exposed semiconductor substrate using the device isolation layer as an etch mask to form a recessed channel region. The recessed channel region allows the channel width and channel length of a transistor to be increased, thereby reducing the occurrence of short channel effects and narrow channel effects in highly integrated semiconductor devices.

    摘要翻译： 一种制造包括鳍状场效应晶体管（Fin-FET）的半导体器件的方法包括：在半导体衬底上形成牺牲棒，对牺牲棒进行构图以在半导体衬底上形成牺牲岛，形成器件隔离层以填充第 牺牲岛，选择性地去除牺牲岛以将牺牲岛下方的半导体衬底暴露出来，并且使用器件隔离层作为蚀刻掩模来各向异性蚀刻暴露的半导体衬底以形成凹陷沟道区。 凹陷沟道区域允许晶体管的沟道宽度和沟道长度增加，从而减少在高度集成的半导体器件中的短沟道效应和窄沟道效应的发生。