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公开(公告)号:US07759787B2
公开(公告)日:2010-07-20
申请号:US11935834
申请日:2007-11-06
IPC分类号: H01L23/053 , H01L23/12
CPC分类号: H05K1/0271 , H01L23/49833 , H01L23/49838 , H01L2924/0002 , H05K3/0005 , H05K3/4644 , H05K2201/09136 , H05K2201/09227 , H05K2203/1572 , Y10T29/49004 , Y10T29/49155 , H01L2924/00
摘要: A pattern matched pair of a front metal interconnect layer and a back metal interconnect layer having matched thermal expansion coefficients are provided for a reduced warp packaging substrate. Metal interconnect layers containing a high density of wiring and complex patterns are first developed so that interconnect structures for signal transmission are optimized for electrical performance. Metal interconnect layers containing a low density wiring and relatively simple patterns are then modified to match the pattern of a mirror image metal interconnect layer located on the opposite side of the core and the same number of metal interconnect layer away from the core. During this pattern-matching process, the contiguity of electrical connection in the metal layers with a low density wiring may become disrupted. The disruption is healed by an additional design step in which the contiguity of the electrical connection in the low density is reestablished.
摘要翻译: 提供具有匹配的热膨胀系数的前金属互连层和背金属互连层的图案匹配对,用于经缩短的经向包装基板。 首先开发了包含高密度布线和复杂图案的金属互连层,使得用于信号传输的互连结构被优化用于电性能。 然后修改包含低密度布线和相对简单图案的金属互连层,以匹配位于芯的相对侧上的镜像金属互连层的图案和与芯相距相同数量的金属互连层。 在这种模式匹配过程中,具有低密度布线的金属层中的电连接的连续性可能会被破坏。 通过额外的设计步骤来治愈中断,其中重新建立低密度电连接的邻接性。
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公开(公告)号:US20090114429A1
公开(公告)日:2009-05-07
申请号:US11935834
申请日:2007-11-06
CPC分类号: H05K1/0271 , H01L23/49833 , H01L23/49838 , H01L2924/0002 , H05K3/0005 , H05K3/4644 , H05K2201/09136 , H05K2201/09227 , H05K2203/1572 , Y10T29/49004 , Y10T29/49155 , H01L2924/00
摘要: A pattern matched pair of a front metal interconnect layer and a back metal interconnect layer having matched thermal expansion coefficients are provided for a reduced warp packaging substrate. Metal interconnect layers containing a high density of wiring and complex patterns are first developed so that interconnect structures for signal transmission are optimized for electrical performance. Metal interconnect layers containing a low density wiring and relatively simple patterns are then modified to match the pattern of a mirror image metal interconnect layer located on the opposite side of the core and the same number of metal interconnect layer away from the core. During this pattern-matching process, the contiguity of electrical connection in the metal layers with a low density wiring may become disrupted. The disruption is healed by an additional design step in which the contiguity of the electrical connection in the low density is reestablished.
摘要翻译: 提供具有匹配的热膨胀系数的前金属互连层和背金属互连层的图案匹配对,用于经缩短的经向包装基板。 首先开发了包含高密度布线和复杂图案的金属互连层,使得用于信号传输的互连结构被优化用于电性能。 然后修改包含低密度布线和相对简单图案的金属互连层,以匹配位于芯的相对侧上的镜像金属互连层的图案和与芯相距相同数量的金属互连层。 在这种模式匹配过程中,具有低密度布线的金属层中的电连接的连续性可能会被破坏。 通过额外的设计步骤来治愈中断,其中重新建立低密度电连接的邻接性。
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公开(公告)号:US20100218364A1
公开(公告)日:2010-09-02
申请号:US12775970
申请日:2010-05-07
IPC分类号: H05K3/22
CPC分类号: H05K1/0271 , H01L23/49833 , H01L23/49838 , H01L2924/0002 , H05K3/0005 , H05K3/4644 , H05K2201/09136 , H05K2201/09227 , H05K2203/1572 , Y10T29/49004 , Y10T29/49155 , H01L2924/00
摘要: A pattern matched pair of a front metal interconnect layer and a back metal interconnect layer having matched thermal expansion coefficients are provided for a reduced warp packaging substrate. Metal interconnect layers containing a high density of wiring and complex patterns are first developed so that interconnect structures for signal transmission are optimized for electrical performance. Metal interconnect layers containing a low density wiring and relatively simple patterns are then modified to match the pattern of a mirror image metal interconnect layer located on the opposite side of the core and the same number of metal interconnect layer away from the core. During this pattern-matching process, the contiguity of electrical connection in the metal layers with a low density wiring may become disrupted. The disruption is healed by an additional design step in which the contiguity of the electrical connection in the low density is reestablished.
摘要翻译: 提供具有匹配的热膨胀系数的前金属互连层和背金属互连层的图案匹配对,用于经缩短的经向包装基板。 首先开发了包含高密度布线和复杂图案的金属互连层,使得用于信号传输的互连结构被优化用于电性能。 然后修改包含低密度布线和相对简单图案的金属互连层,以匹配位于芯的相对侧上的镜像金属互连层的图案和与芯相距相同数量的金属互连层。 在这种模式匹配过程中,具有低密度布线的金属层中的电连接的连续性可能会被破坏。 通过额外的设计步骤来治愈中断,其中重新建立低密度电连接的邻接性。
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公开(公告)号:US07901998B2
公开(公告)日:2011-03-08
申请号:US12775970
申请日:2010-05-07
CPC分类号: H05K1/0271 , H01L23/49833 , H01L23/49838 , H01L2924/0002 , H05K3/0005 , H05K3/4644 , H05K2201/09136 , H05K2201/09227 , H05K2203/1572 , Y10T29/49004 , Y10T29/49155 , H01L2924/00
摘要: A pattern matched pair of a front metal interconnect layer and a back metal interconnect layer having matched thermal expansion coefficients are provided for a reduced warp packaging substrate. Metal interconnect layers containing a high density of wiring and complex patterns are first developed so that interconnect structures for signal transmission are optimized for electrical performance. Metal interconnect layers containing a low density wiring and relatively simple patterns are then modified to match the pattern of a mirror image metal interconnect layer located on the opposite side of the core and the same number of metal interconnect layer away from the core. During this pattern-matching process, the contiguity of electrical connection in the metal layers with a low density wiring may become disrupted. The disruption is healed by an additional design step in which the contiguity of the electrical connection in the low density is reestablished.
摘要翻译: 提供具有匹配的热膨胀系数的前金属互连层和背金属互连层的图案匹配对,用于经缩短的经向包装基板。 首先开发了包含高密度布线和复杂图案的金属互连层,使得用于信号传输的互连结构被优化用于电性能。 然后修改包含低密度布线和相对简单图案的金属互连层,以匹配位于芯的相对侧上的镜像金属互连层的图案和与芯相距相同数量的金属互连层。 在这种模式匹配过程中,具有低密度布线的金属层中的电连接的连续性可能会被破坏。 通过额外的设计步骤来治愈中断,其中重新建立低密度电连接的邻接性。
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5.
公开(公告)号:US20090265028A1
公开(公告)日:2009-10-22
申请号:US12107064
申请日:2008-04-21
申请人: Sri M. Sri-Jayantha , Arun Sharma , Vijayeshwar D. Khanna , Hien P. Dang , David J. Russell , Douglas O. Powell
发明人: Sri M. Sri-Jayantha , Arun Sharma , Vijayeshwar D. Khanna , Hien P. Dang , David J. Russell , Douglas O. Powell
IPC分类号: G06F19/00
CPC分类号: H05K3/0005 , H05K1/0271 , H05K3/4602 , H05K3/4626 , H05K2201/0191 , H05K2201/09136
摘要: A process for large scale production of a laminated organic substrate having reduced thermal warp.
摘要翻译: 用于大规模生产具有降低的热翘曲的层压有机基材的方法。
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公开(公告)号:US07777301B2
公开(公告)日:2010-08-17
申请号:US12099412
申请日:2008-04-08
申请人: David Questad , Vijayeshwar D. Khanna , Jennifer V. Muncy , Arun Sharma , Sri M. Sri-Jayantha , Lorenzo Valdevit
发明人: David Questad , Vijayeshwar D. Khanna , Jennifer V. Muncy , Arun Sharma , Sri M. Sri-Jayantha , Lorenzo Valdevit
IPC分类号: H01L23/48
CPC分类号: H01L28/40 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00011 , H01L2924/00014 , H01L2924/15174 , H01L2924/15311 , H05K1/0231 , H05K1/0271 , H05K1/111 , H05K3/3436 , H05K3/3442 , H05K2201/09036 , H05K2201/10015 , H05K2201/10727 , Y02P70/613 , Y10T29/4913 , Y10T428/24479 , H01L2224/0401 , H01L2924/00
摘要: A method of mounting an electronic component on a substrate includes forming at least one trench in a surface of the substrate. The trenches formed in the substrate reduce a stiffness of the substrate, which provides less resistance to shear. Accordingly, the trenches reduce the amount of strain on the joints, which mount the electronic component to the substrate, which enhances the life of the joints.
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7.
公开(公告)号:US08054630B2
公开(公告)日:2011-11-08
申请号:US12030260
申请日:2008-02-13
申请人: David Questad , Vijayeshwar D. Khanna , Jennifer V. Muney , Arun Sharma , Sri M. Sri-Jayantha , Lorenzo Valdevit
发明人: David Questad , Vijayeshwar D. Khanna , Jennifer V. Muney , Arun Sharma , Sri M. Sri-Jayantha , Lorenzo Valdevit
IPC分类号: H05K7/20
CPC分类号: H01L28/40 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00011 , H01L2924/00014 , H01L2924/15174 , H01L2924/15311 , H05K1/0231 , H05K1/0271 , H05K1/111 , H05K3/3436 , H05K3/3442 , H05K2201/09036 , H05K2201/10015 , H05K2201/10727 , Y02P70/613 , Y10T29/4913 , Y10T428/24479 , H01L2224/0401 , H01L2924/00
摘要: A method of mounting an electronic component on a substrate includes forming at least one trench in a surface of the substrate. The trenches formed in the substrate reduce a stiffness of the substrate, which provides less resistance to shear. Accordingly, the trenches reduce the amount of strain on the joints, which mount the electronic component to the substrate, which enhances the life of the joints.
摘要翻译: 将电子部件安装在基板上的方法包括在基板的表面中形成至少一个沟槽。 形成在衬底中的沟槽降低了衬底的刚度,这提供了较小的剪切阻力。 因此,沟槽减少了将电子部件安装到基板上的接头上的应变量,这增加了接头的寿命。
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8.
公开(公告)号:US20090085161A1
公开(公告)日:2009-04-02
申请号:US12030274
申请日:2008-02-13
申请人: David Questad , Vijayeshwar D. Khanna , Jennifer V. Muney , Arun Sharma , Sri M. Sri-Jayantha , Lorenzo Valdevit
发明人: David Questad , Vijayeshwar D. Khanna , Jennifer V. Muney , Arun Sharma , Sri M. Sri-Jayantha , Lorenzo Valdevit
IPC分类号: H01L29/00
CPC分类号: H01L28/40 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00011 , H01L2924/00014 , H01L2924/15174 , H01L2924/15311 , H05K1/0231 , H05K1/0271 , H05K1/111 , H05K3/3436 , H05K3/3442 , H05K2201/09036 , H05K2201/10015 , H05K2201/10727 , Y02P70/613 , Y10T29/4913 , Y10T428/24479 , H01L2224/0401 , H01L2924/00
摘要: A method of mounting an electronic component on a substrate includes forming at least one trench in a surface of the substrate. The trenches formed in the substrate reduce a stiffness of the substrate, which provides less resistance to shear. Accordingly, the trenches reduce the amount of strain on the joints, which mount the electronic component to the substrate, which enhances the life of the joints.
摘要翻译: 将电子部件安装在基板上的方法包括在基板的表面中形成至少一个沟槽。 形成在衬底中的沟槽降低了衬底的刚度,这提供了较小的剪切阻力。 因此,沟槽减少了将电子部件安装到基板上的接头上的应变量,这增加了接头的寿命。
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9.
公开(公告)号:US20080226875A1
公开(公告)日:2008-09-18
申请号:US12099412
申请日:2008-04-08
申请人: David Questad , Vijayeshwar D. Khanna , Jennifer V. Muncy , Arun Sharma , Sri M. Sri-Jayantha , Lorenzo Valdevit
发明人: David Questad , Vijayeshwar D. Khanna , Jennifer V. Muncy , Arun Sharma , Sri M. Sri-Jayantha , Lorenzo Valdevit
IPC分类号: B32B3/00
CPC分类号: H01L28/40 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00011 , H01L2924/00014 , H01L2924/15174 , H01L2924/15311 , H05K1/0231 , H05K1/0271 , H05K1/111 , H05K3/3436 , H05K3/3442 , H05K2201/09036 , H05K2201/10015 , H05K2201/10727 , Y02P70/613 , Y10T29/4913 , Y10T428/24479 , H01L2224/0401 , H01L2924/00
摘要: A method of mounting an electronic component on a substrate includes forming at least one trench in a surface of the substrate. The trenches formed in the substrate reduce a stiffness of the substrate, which provides less resistance to shear. Accordingly, the trenches reduce the amount of strain on the joints, which mount the electronic component to the substrate, which enhances the life of the joints.
摘要翻译: 将电子部件安装在基板上的方法包括在基板的表面中形成至少一个沟槽。 形成在衬底中的沟槽降低了衬底的刚度,这提供了较小的剪切阻力。 因此,沟槽减少了将电子部件安装到基板上的接头上的应变量,这增加了接头的寿命。
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公开(公告)号:US20080205023A1
公开(公告)日:2008-08-28
申请号:US11679407
申请日:2007-02-27
申请人: Vijayeshwar D. Khanna , Jennifer V. Muncy , Arun Sharma , Sri M. Sri-Jayantha , Lorenzo Valdevit , David Questad
发明人: Vijayeshwar D. Khanna , Jennifer V. Muncy , Arun Sharma , Sri M. Sri-Jayantha , Lorenzo Valdevit , David Questad
CPC分类号: H01L28/40 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00011 , H01L2924/00014 , H01L2924/15174 , H01L2924/15311 , H05K1/0231 , H05K1/0271 , H05K1/111 , H05K3/3436 , H05K3/3442 , H05K2201/09036 , H05K2201/10015 , H05K2201/10727 , Y02P70/613 , Y10T29/4913 , Y10T428/24479 , H01L2224/0401 , H01L2924/00
摘要: A method of mounting an electronic component on a substrate includes forming at least one trench in a surface of the substrate. The trenches formed in the substrate reduce a stiffness of the substrate, which provides less resistance to shear. Accordingly, the trenches reduce the amount of strain on the joints, which mount the electronic component to the substrate, which enhances the life of the joints.
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