公开(公告)号：US20160380326A1

公开(公告)日：2016-12-29

申请号：US14752639

申请日：2015-06-26

申请人： Stephen H. Hall ,  Vijay Kasturi ,  Michael T. Hamann

发明人： Stephen H. Hall ,  Vijay Kasturi ,  Michael T. Hamann

IPC分类号： H01P3/08 ,  H05K1/02

CPC分类号： H05K1/028 ,  H01P11/003 ,  H05K1/148

摘要： Techniques and mechanisms for enabling small radius bending of a flexible circuit. In an embodiment, the flexible circuit includes a first section, a second section and a third section between the first section and second section. Stacked structures of the first section include a first trace portion and a first conductor, and stacked structures of the second section include a second trace portion and a second conductor. In another embodiment, a first span structure of the third section exchanges a first signal between the first trace portion and the second trace portion while the first conductor and the second conductor are maintained at a reference potential. While the first signal is exchanged, a second span structure of the third section—coplanar with the first span structure—is maintained at the reference potential or propagates a second signal complementary to the first signal.

摘要翻译： 用于实现柔性电路的小半径弯曲的技术和机构。 在一个实施例中，柔性电路包括第一部分，第二部分和第一部分与第二部分之间的第三部分。 第一部分的堆叠结构包括第一迹线部分和第一导体，并且第二部分的堆叠结构包括第二迹线部分和第二导体。 在另一个实施例中，第三部分的第一跨距结构在第一导体和第二导体保持在参考电位的同时在第一迹线部分和第二迹线部分之间交换第一信号。 当第一信号被交换时，与第一跨度结构共面的第三部分的第二跨度结构保持在参考电位或传播与第一信号互补的第二信号。

公开(公告)号：US20170290154A1

公开(公告)日：2017-10-05

申请号：US15089303

申请日：2016-04-01

申请人： Khang Choong Yong ,  Stephen H. Hall ,  Tin Poay Chuah ,  Boon Ping Koh ,  Eng Huat Goh

发明人： Khang Choong Yong ,  Stephen H. Hall ,  Tin Poay Chuah ,  Boon Ping Koh ,  Eng Huat Goh

IPC分类号： H05K1/14 ,  H01L25/18 ,  H05K3/30 ,  H05K1/02 ,  H05K3/36 ,  H05K1/18 ,  H05K9/00

CPC分类号： H05K1/147 ,  G06K9/0002 ,  H01L25/18 ,  H05K1/0218 ,  H05K1/181 ,  H05K3/363 ,  H05K9/0024 ,  H05K2201/047 ,  H05K2201/056 ,  H05K2201/10159

摘要： Three-dimensional (3-D) volumetric board architectural design provides technical solutions to technical problems facing miniaturization of circuit boards. The 3-D volumetric architecture includes using more of the unused volume in the vertical dimension (e.g., Z-dimension) to increase the utilization of the total circuit board volume. The 3-D volumetric architecture is realized by mounting components on a first PCB and on a second PCB, and inverting and suspending the second PCB above the first PCB. The use of 3-D volumetric board architectural design further enables formation of a shielded FEMIE, providing shielding and improved volumetric use with little or no reduction in system performance or increase in system Z-height.

公开(公告)号：US5450900A

公开(公告)日：1995-09-19

申请号：US271609

申请日：1994-07-07

申请人： Ronald Schalla ,  Ronald M. Smith ,  Stephen H. Hall ,  John E. Smart

发明人： Ronald Schalla ,  Ronald M. Smith ,  Stephen H. Hall ,  John E. Smart

IPC分类号： E21B43/12 ,  E21B49/08 ,  E21B43/00

CPC分类号： E21B49/084 ,  E21B43/121

摘要： The present invention specifically permits purging and/or sampling of a well but only removing, at most, about 25% of the fluid volume compared to conventional methods and, at a minimum, removing none of the fluid volume from the well.The invention is an isolation assembly that is inserted into the well. The isolation assembly is designed so that only a volume of fluid between the outside diameter of the isolation assembly and the inside diameter of the well over a fluid column height from the bottom of the well to the top of the active portion (lower annulus) is removed. A seal may be positioned above the active portion thereby sealing the well and preventing any mixing or contamination of inlet fluid with fluid above the packer. Purged well fluid is stored in a riser above the packer. Ports in the wall of the isolation assembly permit purging and sampling of the lower annulus along the height of the active portion.

摘要翻译： 本发明具体允许清洗和/或取样一个井，但与常规方法相比只能去除至多约25％的流体体积，并且至少从井中不去除流体体积。 本发明是插入井中的隔离组件。 隔离组件被设计成使得在隔离组件的外径和从井的底部到活动部分（下环空间）的顶部之间的流体柱高度的井的内径之间仅有一定体积的流体是 删除。 密封件可以位于活性部分上方，从而密封井，并防止进口流体与封隔器上方的流体混合或污染。 净化的流体储存在封隔器上方的提升管中。 隔离组件的壁中的端口允许沿着有效部分的高度清洗和取样下环。

公开(公告)号：US20140181357A1

公开(公告)日：2014-06-26

申请号：US13726748

申请日：2012-12-26

申请人： Stephen H. Hall ,  Chaitanya Sreerama ,  Jason A. Mix ,  Michael W. Leddige ,  Jose A. Sanchez Sanchez ,  Olufemi B. Oluwafemi ,  Paul G. Huray ,  MAYNARD C. FALCONER

发明人： Stephen H. Hall ,  Chaitanya Sreerama ,  Jason A. Mix ,  Michael W. Leddige ,  Jose A. Sanchez Sanchez ,  Olufemi B. Oluwafemi ,  Paul G. Huray ,  MAYNARD C. FALCONER

IPC分类号： G06F13/40

CPC分类号： G06F13/4022

摘要： Techniques for encoding data are described herein. An example of a device in accordance with the present techniques includes a signaling module coupled to a plurality of digital inputs. The signaling module is to encode data received at the plurality of digital inputs to generate encoded data. Based on the encoded data, the signaling module can drive line voltages on a plurality of signal lines of a bus. Each one of the plurality of line voltages corresponds to a weighted sum of the data received at the plurality of digital inputs.

摘要翻译： 本文描述了用于编码数据的技术。 根据本技术的设备的示例包括耦合到多个数字输入的信令模块。 信令模块是对在多个数字输入端接收的数据进行编码，以生成编码数据。 基于编码数据，信令模块可以驱动总线的多个信号线上的线路电压。 多个线路电压中的每一个对应于在多个数字输入端接收的数据的加权和。

公开(公告)号：US20100202118A1

公开(公告)日：2010-08-12

申请号：US12757356

申请日：2010-04-09

申请人： Tao Liang ,  Stephen H. Hall ,  Howard Heck ,  Gary A. Brist ,  Bryce Horine

发明人： Tao Liang ,  Stephen H. Hall ,  Howard Heck ,  Gary A. Brist ,  Bryce Horine

IPC分类号： H05K1/18

CPC分类号： H05K1/0245 ,  H05K1/0366 ,  H05K2201/029 ,  H05K2201/09236

摘要： An article of manufacture includes a circuit board and a pair of traces on or in the circuit board. The pair of traces includes a first trace and a second trace. The first trace includes a first segment and a second segment continuously joined to the first segment. The first segment coincides with a first longitudinal axis. The second trace includes a first segment that runs alongside the first segment of the first trace. The second trace also includes a second segment that runs alongside the second segment of the first trace. The second segment of the second trace is continuously joined to the first segment of the second trace. The second segment of the second trace coincides with the first longitudinal axis.

摘要翻译： 制造品包括电路板和电路板上或电路板中的一对迹线。 该对轨迹包括第一轨迹和第二轨迹。 第一迹线包括连续地连接到第一段的第一段和第二段。 第一段与第一纵向轴线重合。 第二个跟踪包括与第一个跟踪的第一个段一起运行的第一个段。 第二轨迹还包括与第一轨迹的第二段一起运行的第二段。 第二迹线的第二段连续地连接到第二迹线的第一段。 第二轨迹的第二段与第一纵向轴线重合。

公开(公告)号：US20090080832A1

公开(公告)日：2009-03-26

申请号：US12313320

申请日：2008-11-18

申请人： Bryce D. Horine ,  Gary A. Brist ,  Stephen H. Hall

发明人： Bryce D. Horine ,  Gary A. Brist ,  Stephen H. Hall

IPC分类号： G02B6/12 ,  B29C65/48 ,  G02B6/10

CPC分类号： H05K1/024 ,  H01P3/121 ,  H01P11/002 ,  H05K3/4611 ,  H05K3/4614 ,  H05K3/462 ,  H05K2201/037 ,  H05K2201/0379 ,  H05K2201/09981 ,  Y10T156/1002

摘要： In some embodiments a channel is formed in printed circuit board material, the formed channel is plated to form at least two side walls of a quasi-waveguide, and printed circuit board material is laminated to the plated channel using thermoset adhesive. Other embodiments are described and claimed.

摘要翻译： 在一些实施例中，通道形成在印刷电路板材料中，形成的通道被电镀以形成准波导的至少两个侧壁，并且使用热固性粘合剂将印刷电路板材料层压到电镀通道上。 描述和要求保护其他实施例。

公开(公告)号：US20080308306A1

公开(公告)日：2008-12-18

申请号：US12193298

申请日：2008-08-18

申请人： Tao Liang ,  Stephen H. Hall ,  Howard Heck ,  Gary A. Brist ,  Bryce Horine

发明人： Tao Liang ,  Stephen H. Hall ,  Howard Heck ,  Gary A. Brist ,  Bryce Horine

IPC分类号： H05K1/03

CPC分类号： H05K1/0245 ,  H05K1/0366 ,  H05K2201/029 ,  H05K2201/09236

摘要： An article of manufacture includes a circuit board and a pair of traces on or in the circuit board. The pair of traces includes a first trace and a second trace. The first trace includes a first segment and a second segment continuously joined to the first segment. The first segment coincides with a first longitudinal axis. The second trace includes a first segment that runs alongside the first segment of the first trace. The second trace also includes a second segment that runs alongside the second segment of the first trace. The second segment of the second trace is continuously joined to the first segment of the second trace. The second segment of the second trace coincides with the first longitudinal axis.

摘要翻译： 制造品包括电路板和电路板上或电路板中的一对迹线。 该对轨迹包括第一轨迹和第二轨迹。 第一迹线包括连续地连接到第一段的第一段和第二段。 第一段与第一纵向轴线重合。 第二个跟踪包括与第一个跟踪的第一个段一起运行的第一个段。 第二轨迹还包括与第一轨迹的第二段一起运行的第二段。 第二迹线的第二段连续地连接到第二迹线的第一段。 第二轨迹的第二段与第一纵向轴线重合。

公开(公告)号：US07020792B2

公开(公告)日：2006-03-28

申请号：US10135131

申请日：2002-04-30

申请人： Stephen H. Hall

发明人： Stephen H. Hall

IPC分类号： G06F13/42 ,  G06F5/00 ,  H03K5/13 ,  H03K11/26

CPC分类号： H04L25/03038

摘要： A method and apparatus is described that may be utilized to equalize modal velocity changes on a data bus. Modal velocity changes may be equalized by use of variable delays that may be used to equalize modal velocity changes.

公开(公告)号：US06788222B2

公开(公告)日：2004-09-07

申请号：US09759245

申请日：2001-01-16

申请人： Stephen H. Hall ,  Michael W. Leddige

发明人： Stephen H. Hall ,  Michael W. Leddige

IPC分类号： H03M700

CPC分类号： H03M13/00

摘要： A low weight encoding circuit of a power delivery system for encoding data sent out on an I/O bus with minimal current drawn so as to minimize signal and timing distortions. Such a low weight encoding circuit comprises a current balance tester arranged to test whether a predetermined number of data bits is current balanced; a current balance encoder and decode bit generator arranged to encode data bits and generate encoded data and corresponding decode bits if the predetermined number of data bits is not current balanced; and a latch arranged to latch either the data bits, via an I/O bus, if said predetermined number of data bits is current balanced or the encoded data and corresponding decode bits, via the I/O bus, if the predetermined number of data bits is not current balanced.

摘要翻译： 一种功率传递系统的低权重编码电路，用于以最小的电流来对在I / O总线上发送的数据进行编码，以最小化信号和定时失真。 这样一个低权重编码电路包括一个当前平衡测试器，其被布置成测试预定数量的数据位是否是电流平衡的; 电流平衡编码器和解码位发生器，其布置成如果预定数量的数据位不是电流平衡则编码数据位并产生编码数据和对应的解码位; 以及锁存器，其经由I / O总线经由I / O总线来锁存数据位，如果所述预定数量的数据位是电流平衡或经过I / O总线的编码数据和对应的解码位，则如果预定数量的数据 位不是电流平衡。

公开(公告)号：US06737883B2

公开(公告)日：2004-05-18

申请号：US10015712

申请日：2001-12-17

申请人： Stephen H. Hall

发明人： Stephen H. Hall

IPC分类号： H03K19003

CPC分类号： G06F13/4072

摘要： An apparatus includes a substrate, a ground plane on the substrate, the ground plane having a slot, transmission lines lying over the slot, and data processing agents each connected to one of the transmission lines. A method includes inducing a transient return current on a reference plane in response to a driving agent sourcing a current being representative of binary data onto a first transmission line, the current being representative of binary data, propagating energy of the transient return current to a slot in the reference plane, inducing a transient voltage pulse onto a second transmission line connected to a receiving agent when the propagating energy encounters the second transmission line and generating a binary digital signal in the receiving agent from the transient voltage pulse received on the second transmission line.

摘要翻译： 一种装置包括基板，基板上的接地平面，具有槽的接地平面，位于槽上方的传输线，以及各自连接到传输线之一的数据处理代理。 一种方法包括响应于将表示二进制数据的电流提供到第一传输线上的驱动代理，在参考平面上引起瞬时返回电流，该电流代表二进制数据，将瞬态返回电流的能量传播到一个时隙 在参考平面中，当传播能量遇到第二传输线并且在接收代理中从在第二传输线上接收的瞬态电压脉冲产生二进制数字信号时，将瞬态电压脉冲引导到连接到接收代理的第二传输线上 。