公开(公告)号：US08787028B2

公开(公告)日：2014-07-22

申请号：US13677432

申请日：2012-11-15

Applicant: TDK Corporation

Inventor： Yuhei Horikawa ,  Shin Fujita ,  Kenichi Yoshida ,  Hisayuki Abe ,  Makoto Orikasa ,  Hideyuki Seike

IPC: H05K7/00 ,  H05K1/02 ,  H01R43/02

CPC classification number: H05K1/11 ,  H01R4/02 ,  H01R43/00 ,  H05K1/111 ,  H05K1/141 ,  H05K3/244 ,  H05K3/3436 ,  H05K3/3494 ,  Y02P70/613 ,  Y10T29/49204

Abstract: The electronic device includes a terminal structure and a printed circuit board including the terminal structure. The terminal structure includes a solder-joint conductor region placed on a wiring conductor, an intermediate layer contacting with the conductor region, and a solder region contacting with the intermediate layer. The intermediate layer includes an intermetallic compound including tin and at least one of copper and nickel as principal components. When the indentation elastic modulus of the conductor region is E1 and the indentation elastic modulus of the intermediate layer is E2, the ratio of E1 to E2 is equal to or more than 0.8 and equal to or less than 1.5.

Abstract translation: 电子设备包括端子结构和包括端子结构的印刷电路板。 端子结构包括放置在布线导体上的焊点导体区域，与导体区域接触的中间层以及与中间层接触的焊料区域。 中间层包括包含锡和铜和镍中的至少一种作为主要成分的金属间化合物。 当导体区域的压痕弹性模量为E1，中间层的压痕弹性模量为E2时，E1与E2的比例等于或大于0.8且等于或小于1.5。

公开(公告)号：US09257402B2

公开(公告)日：2016-02-09

申请号：US13960330

申请日：2013-08-06

Applicant: TDK CORPORATION

Inventor： Kenichi Yoshida ,  Makoto Orikasa ,  Hideyuki Seike ,  Yuhei Horikawa ,  Hisayuki Abe

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L24/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05571 ,  H01L2224/05655 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13076 ,  H01L2224/13111 ,  H01L2924/00014 ,  H01L2224/05572 ,  H01L2924/00015 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A preferred terminal structure comprises a base material; an electrode formed on the base material; an insulating covering layer formed on the base material and on the electrode and having an opening exposing at least part of the electrode; an under bump metal layer containing Ni, formed in a region in the opening on the electrode so that an upper surface of the metal layer is at a position lower than an upper surface of the insulating covering layer in a peripheral edge portion of the opening; and a dome-shaped bump containing Sn and Ti, formed in a region in the opening on the under bump metal layer, wherein an end portion of a boundary between the under bump metal layer and the bump is in contact with an inner wall of the opening portion in the insulating covering layer.

Abstract translation: 优选的端子结构包括基材; 形成在基材上的电极; 绝缘覆盖层，形成在所述基底材料上和所述电极上，并且具有暴露所述电极的至少一部分的开口; 在所述电极的开口部的区域形成含有Ni的下凸块金属层，使得所述金属层的上表面位于比所述开口的周缘部的绝缘覆盖层的上表面低的位置; 以及形成在下凸块金属层的开口部的区域中的包含Sn和Ti的圆顶状的凸部，其中，下凸块状金属层与凸块之间的边界的端部与内凸块 绝缘覆盖层的开口部。

公开(公告)号：US09177687B2

公开(公告)日：2015-11-03

申请号：US13677509

申请日：2012-11-15

Applicant: TDK CORPORATION

Inventor： Kenichi Yoshida ,  Yuhei Horikawa ,  Makoto Orikasa ,  Hideyuki Seike

IPC: B32B15/01 ,  H01B1/02 ,  C22C5/04 ,  C23C18/16 ,  C23C18/00 ,  C25D3/00 ,  C25D5/00 ,  C23C18/34 ,  C23C18/44 ,  C23C18/54

CPC classification number: H01B1/026 ,  C22C5/04 ,  C23C18/1651 ,  C23C18/34 ,  C23C18/44 ,  C23C18/54 ,  H01B1/02 ,  Y10T428/12701 ,  Y10T428/12722 ,  Y10T428/12778 ,  Y10T428/12861 ,  Y10T428/12889 ,  Y10T428/12903

Abstract: A coating for a conductor, the coating having a layered structure of a palladium layer. The palladium layer has a crystal plane whose orientation rate is 65% or more, which means 65% or more of the crystal planes of the palladium layer are aligned to this crystal plane. Preferably the crystal plane whose orientation rate is 65% or more in the coating is the (111) plane or (200) plane.

Abstract translation: 一种用于导体的涂层，该涂层具有钯层的层状结构。 钯层具有取向率为65％以上的晶面，这意味着钯层的65％以上的晶面与该晶面对准。 优选地，涂层中取向率为65％以上的晶面是（111）面或（200）面。

公开(公告)号：US20130135834A1

公开(公告)日：2013-05-30

申请号：US13677432

申请日：2012-11-15

Applicant: TDK CORPORATION

Inventor： Yuhei Horikawa ,  Shin Fujita ,  Kenichi Yoshida ,  Hisayuki Abe ,  Makoto Orikasa ,  Hideyuki Seike

IPC: H05K1/11 ,  H01R43/00 ,  H01R4/02

CPC classification number: H05K1/11 ,  H01R4/02 ,  H01R43/00 ,  H05K1/111 ,  H05K1/141 ,  H05K3/244 ,  H05K3/3436 ,  H05K3/3494 ,  Y02P70/613 ,  Y10T29/49204

Abstract: The electronic device includes a terminal structure and a printed circuit board including the terminal structure. The terminal structure includes a solder-joint conductor region placed on a wiring conductor, an intermediate layer contacting with the conductor region, and a solder region contacting with the intermediate layer. The intermediate layer includes an intermetallic compound including tin and at least one of copper and nickel as principal components. When the indentation elastic modulus of the conductor region is E1 and the indentation elastic modulus of the intermediate layer is E2, the ratio of E1 to E2 is equal to or more than 0.8 and equal to or less than 1.5.

Abstract translation: 电子设备包括端子结构和包括端子结构的印刷电路板。 端子结构包括放置在布线导体上的焊点导体区域，与导体区域接触的中间层以及与中间层接触的焊料区域。 中间层包括包含锡和铜和镍中的至少一种作为主要成分的金属间化合物。 当导体区域的压痕弹性模量为E1，中间层的压痕弹性模量为E2时，E1与E2的比例等于或大于0.8且等于或小于1.5。

公开(公告)号：US09224706B2

公开(公告)日：2015-12-29

申请号：US13960330

申请日：2013-08-06

Applicant: TDK CORPORATION

Inventor： Kenichi Yoshida ,  Makoto Orikasa ,  Hideyuki Seike ,  Yuhei Horikawa ,  Hisayuki Abe

IPC: H01L23/48 ,  H01L23/00

Abstract: A preferred terminal structure comprises a base material; an electrode formed on the base material; an insulating covering layer formed on the base material and on the electrode and having an opening exposing at least part of the electrode; an under bump metal layer containing Ni, formed in a region in the opening on the electrode so that an upper surface of the metal layer is at a position lower than an upper surface of the insulating covering layer in a peripheral edge portion of the opening; and a dome-shaped bump containing Sn and Ti, formed in a region in the opening on the under bump metal layer, wherein an end portion of a boundary between the under bump metal layer and the bump is in contact with an inner wall of the opening portion in the insulating covering layer.

公开(公告)号：US08970037B2

公开(公告)日：2015-03-03

申请号：US13960291

申请日：2013-08-06

Applicant: TDK Corporation

Inventor： Kenichi Yoshida ,  Makoto Orikasa ,  Hideyuki Seike ,  Yuhei Horikawa ,  Hisayuki Abe

IPC: H01L23/485 ,  H01L23/492 ,  H01L23/00

CPC classification number: H01L24/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05571 ,  H01L2224/05655 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A preferred terminal structure comprises a base material; an electrode formed on the base material; an insulating covering layer formed on the base material and on the electrode and having an opening exposing at least part of the electrode; an under bump metal layer containing Ni, filling the opening on the electrode; and a dome-shaped bump containing Sn and Ti, covering the under bump metal layer, wherein at least part of the under bump metal layer has a portion sandwiched between the external electrode and the insulating covering layer.

Abstract translation: 优选的端子结构包括基材; 形成在基材上的电极; 绝缘覆盖层，形成在所述基底材料上和所述电极上，并且具有暴露所述电极的至少一部分的开口; 含有Ni的下凸块金属层，填充电极上的开口; 以及包含Sn和Ti的圆顶状凸起，覆盖下凸块状金属层，其中至少部分下凸块金属层具有夹在外部电极和绝缘覆盖层之间的部分。

公开(公告)号：US08933336B2

公开(公告)日：2015-01-13

申请号：US13678033

申请日：2012-11-15

Applicant: TDK Corporation

Inventor： Kenichi Yoshida ,  Yuhei Horikawa ,  Makoto Orikasa ,  Hideyuki Seike

IPC: H01B1/00 ,  H01B1/02

CPC classification number: H01B1/02 ,  H01L2224/85444

Abstract: A coating having a layered structure including a palladium layer is provided to a conductor. The highly stable palladium layer is amorphous and contains phosphorus in a concentration ranging from 7.3% by mass to 11.0% by mass. An electronic component may include the conductor coated with the coating. The conductor coated with the coating has superior corrosion resistance and superior reliability in electrical connection with external apparatuses.

Abstract translation: 具有包括钯层的层状结构的涂层被提供给导体。 高度稳定的钯层为无定形，含有浓度为7.3质量％〜11.0质量％的磷。 电子部件可以包括涂覆有涂层的导体。 涂覆有涂层的导体具有优异的耐腐蚀性和与外部设备电连接的优异的可靠性。

公开(公告)号：US10354973B2

公开(公告)日：2019-07-16

申请号：US16037537

申请日：2018-07-17

Applicant: TDK CORPORATION

Inventor： Makoto Orikasa ,  Hideyuki Seike ,  Yuhei Horikawa ,  Hisayuki Abe

IPC: H01L21/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: A method for producing a semiconductor chip is a method for producing a semiconductor chip that includes a substrate, a conductive portion formed on the substrate, and a microbump formed on the conductive portion, which includes a smooth surface formation process of forming a smooth surface on the microbump, and the smooth surface formation process includes a heating process of causing a reducing gas to flow in an inert atmosphere into a space where the semiconductor chips are arranged and heated at or higher than a temperature of a melting point of the microbump, and in the heating process, a pressure application member is mounted on the microbump and among principal surfaces of the pressure application member, a principal surface that contacts the microbump is a flat surface.

公开(公告)号：US10163847B2

公开(公告)日：2018-12-25

申请号：US15449361

申请日：2017-03-03

Applicant: TDK CORPORATION

Inventor： Makoto Orikasa ,  Hideyuki Seike ,  Yuhei Horikawa ,  Hisayuki Abe

IPC: H01L21/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: A method for producing a semiconductor package is a method for producing a semiconductor package in which a plurality of semiconductor chips, each of which includes a substrate, conductive portions formed on the substrate, and microbumps formed on the conductive portions, are laminated, which includes a heating process of causing a reducing gas to flow in an inert atmosphere into a space where the semiconductor chips are arranged and heated at or higher than a temperature of a melting point of the microbump, and in the heating process, a pressure application member is mounted on the microbump.

公开(公告)号：US09818736B1

公开(公告)日：2017-11-14

申请号：US15449074

申请日：2017-03-03

Applicant: TDK CORPORATION

Inventor： Makoto Orikasa ,  Hideyuki Seike ,  Yuhei Horikawa ,  Hisayuki Abe

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L25/50 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/13611 ,  H01L2224/16 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2225/1058 ,  H01L2924/15311

Abstract: A method for producing a semiconductor package in which a plurality of semiconductor chips, each of which includes a substrate, conductive portions formed on the substrate, and microbumps formed on the conductive portions, are laminated, which includes a smooth surface formation process of forming a smooth surface on the microbump, a lamination process of laminating three or more of the semiconductor chips by overlaying the microbump of one of the semiconductor chips on the microbump of another one of the semiconductor chips, and a bonding process of bonding the semiconductor chips to each other via the microbumps by heating to melt the microbumps, in which in the lamination process, of one of the semiconductor chips and another one of the semiconductor chips, the smooth surface is formed on at least one of the microbump, and one of the microbump contacts another one of the microbump on the smooth surface.