公开(公告)号：US12072812B2

公开(公告)日：2024-08-27

申请号：US17237391

申请日：2021-04-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. Anderson ,  Joseph Zbiciak ,  Duc Quang Bui ,  Abhijeet Chachad ,  Kai Chirca ,  Naveen Bhoria ,  Matthew D. Pierson ,  Daniel Wu ,  Ramakrishnan Venkatasubramanian

IPC: G06F9/30 ,  G06F7/24 ,  G06F7/487 ,  G06F7/499 ,  G06F7/53 ,  G06F7/57 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F9/48 ,  G06F11/00 ,  G06F11/10 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/1045 ,  G06F17/16 ,  H03H17/06 ,  G06F15/78

CPC classification number: G06F12/1045 ,  G06F7/24 ,  G06F7/487 ,  G06F7/4876 ,  G06F7/49915 ,  G06F7/53 ,  G06F7/57 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/30072 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3856 ,  G06F9/3867 ,  G06F9/3887 ,  G06F9/48 ,  G06F11/00 ,  G06F11/1048 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F17/16 ,  H03H17/0664 ,  G06F9/30018 ,  G06F9/325 ,  G06F9/381 ,  G06F9/3822 ,  G06F11/10 ,  G06F15/7807 ,  G06F15/781 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/602 ,  G06F2212/68

Abstract: Disclosed embodiments include an electronic device having a processor core, a memory, a register, and a data load unit to receive a plurality of data elements stored in the memory in response to an instruction. All of the data elements hare the same data size, which is specified by one or more coding bits. The data load unit includes an address generator to generate addresses corresponding to locations in the memory at which the data elements are located, and a formatting unit to format the data elements. The register is configured to store the formatted data elements, and the processor core is configured to receive the formatted data elements from the register.

公开(公告)号：US11036648B2

公开(公告)日：2021-06-15

申请号：US16227238

申请日：2018-12-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. Anderson ,  Joseph Zbiciak ,  Duc Quang Bui ,  Abhijeet Chachad ,  Kai Chirca ,  Naveen Bhoria ,  Matthew D. Pierson ,  Daniel Wu ,  Ramakrishnan Venkatasubramanian

IPC: G06F9/34 ,  G06F11/00 ,  G06F12/0875 ,  G06F12/1045 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/10 ,  G06F9/32 ,  G06F12/0897 ,  G06F12/0862 ,  G06F12/1009

Abstract: Disclosed embodiments include a data processing apparatus having a processing core, a memory, and a streaming engine. The streaming engine is configured to receive a plurality of data elements stored in the memory and to provide the plurality of data elements as a data stream to the processing core, and includes an address generator to generate addresses corresponding to locations in the memory, a buffer to store the data elements received from the locations in the memory corresponding to the generated addresses, and an output to supply the data elements received from the memory to the processing core as the data stream.

公开(公告)号：USRE46193E1

公开(公告)日：2016-11-01

申请号：US14303262

申请日：2014-06-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Lewis Nardini ,  Jose Luis Flores ,  Abhijeet Chachad ,  Raguram Damodaran ,  Joseph R. M. Zbiciak ,  Gary Swoboda

IPC: G06F1/32

Abstract: An embedded megamodule and an embedded CPU enable power-saving through a combination of hardware and software. The CPU configures the power-down controller (PDC) logic within megamodule and can software trigger a low-power state of logic modules during processor IDLE periods. To wake from this power-down state, a system event is asserted to the CPU through the module interrupt controller. Thus the entry into a low-power state is software-driven during periods of inactivity and power restoration is on system activity that demands the attention of the CPU.

Abstract translation: 嵌入式巨型模块和嵌入式CPU通过硬件和软件的组合实现节能。 CPU在兆模块内配置掉电控制器（PDC）逻辑，并且可以在处理器空闲周期期间软件触发逻辑模块的低功耗状态。 要从此掉电状态唤醒，系统事件将通过模块中断控制器发送到CPU。 因此，进入低功耗状态是在非活动期间进行软件驱动，并且电源恢复是需要CPU注意的系统活动。

公开(公告)号：US20190146790A1

公开(公告)日：2019-05-16

申请号：US16227238

申请日：2018-12-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. Anderson ,  Joseph Zbiciak ,  Duc Quang Bui ,  Abhijeet Chachad ,  Kai Chirca ,  Naveen Bhoria ,  Matthew D. Pierson ,  Daniel Wu ,  Ramakrishnan Venkatasubramanian

IPC: G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/10 ,  G06F9/32 ,  G06F12/0875 ,  G06F12/0897 ,  G06F11/00

Abstract: Disclosed embodiments include a data processing apparatus having a processing core, a memory, and a streaming engine. The streaming engine is configured to receive a plurality of data elements stored in the memory and to provide the plurality of data elements as a data stream to the processing core, and includes an address generator to generate addresses corresponding to locations in the memory, a buffer to store the data elements received from the locations in the memory corresponding to the generated addresses, and an output to supply the data elements received from the memory to the processing core as the data stream.

公开(公告)号：US20240411703A1

公开(公告)日：2024-12-12

申请号：US18813178

申请日：2024-08-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. Anderson ,  Joseph Zbiciak ,  Duc Quang Bui ,  Abhijeet Chachad ,  Kai Chirca ,  Naveen Bhoria ,  Matthew D. Pierson ,  Daniel Wu ,  Ramakrishnan Venkatasubramanian

IPC: G06F12/1045 ,  G06F7/24 ,  G06F7/487 ,  G06F7/499 ,  G06F7/53 ,  G06F7/57 ,  G06F9/30 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F9/48 ,  G06F11/00 ,  G06F11/10 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F15/78 ,  G06F17/16 ,  H03H17/06

Abstract: Disclosed embodiments include an electronic device having a processor core, a memory, a register, and a data load unit to receive a plurality of data elements stored in the memory in response to an instruction. All of the data elements hare the same data size, which is specified by one or more coding bits. The data load unit includes an address generator to generate addresses corresponding to locations in the memory at which the data elements are located, and a formatting unit to format the data elements. The register is configured to store the formatted data elements, and the processor core is configured to receive the formatted data elements from the register.

公开(公告)号：US20210240634A1

公开(公告)日：2021-08-05

申请号：US17237391

申请日：2021-04-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. Anderson ,  Joseph Zbiciak ,  Duc Quang Bui ,  Abhijeet Chachad ,  Kai Chirca ,  Naveen Bhoria ,  Matthew D. Pierson ,  Daniel Wu ,  Ramakrishnan Venkatasubramanian

IPC: G06F12/1045 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/00 ,  G06F11/10 ,  G06F9/32 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/0862 ,  G06F12/1009

Abstract: Disclosed embodiments include an electronic device having a processor core, a memory, a register, and a data load unit to receive a plurality of data elements stored in the memory in response to an instruction. All of the data elements hare the same data size, which is specified by one or more coding bits. The data load unit includes an address generator to generate addresses corresponding to locations in the memory at which the data elements are located, and a formatting unit to format the data elements. The register is configured to store the formatted data elements, and the processor core is configured to receive the formatted data elements from the register.