公开(公告)号：US20220208665A1

公开(公告)日：2022-06-30

申请号：US17139985

申请日：2020-12-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nazila Dadvand ,  Bernardo Gallegos

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package includes a pad and leads, the pad and leads including a base metal predominantly including copper, a first plated metal layer predominantly including nickel in contact with the base metal, and a second plated metal layer predominantly including silver in contact with the first plated metal layer. The first plated metal layer has a first plated metal layer thickness of 0.1 to 5 microns, and the second plated metal layer has a second plated metal layer thickness of 0.2 to 5 microns. The semiconductor package further includes an adhesion promotion coating predominantly including silver oxide in contact with the second plated metal layer opposite the first plated metal layer, a semiconductor die mounted on the pad, a wire bond extending between the semiconductor die and a lead of the leads, and a mold compound covering the semiconductor die and the wire bond.

公开(公告)号：US20240224415A1

公开(公告)日：2024-07-04

申请号：US18603099

申请日：2024-03-12

Applicant: Texas Instruments Incorporated

Inventor： Tianyi Luo ,  Osvaldo Jorge Lopez ,  Jonathan Almeria Noquil ,  Satyendra Singh Chauhan ,  Bernardo Gallegos

IPC: H05K1/02 ,  H01L21/50 ,  H01L21/60 ,  H01L23/00 ,  H01L23/538

CPC classification number: H05K1/0271 ,  H01L21/50 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/14 ,  H01L2021/60097 ,  H01L2224/16225

Abstract: In a described example, an apparatus includes: a package substrate having a planar die mount surface; recesses extending into the planar die mount surface; and a semiconductor device die flip chip mounted to the package substrate on the planar die mount surface, the semiconductor device die having post connects having proximate ends on bond pads on an active surface of the semiconductor device die, and extending to distal ends away from the semiconductor device die having solder bumps, wherein the solder bumps form solder joints to the package substrate within the recesses.

公开(公告)号：US11848258B2

公开(公告)日：2023-12-19

申请号：US17139985

申请日：2020-12-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nazila Dadvand ,  Bernardo Gallegos

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49582 ,  H01L21/4825 ,  H01L21/4835 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/4952 ,  H01L23/49513 ,  H01L23/562 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/48465 ,  H01L2224/48639 ,  H01L2224/48655 ,  H01L2224/48739 ,  H01L2224/48755 ,  H01L2224/48839 ,  H01L2224/48855 ,  H01L2224/85205 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/15747 ,  H01L2924/35121

Abstract: A semiconductor package includes a pad and leads, the pad and leads including a base metal predominantly including copper, a first plated metal layer predominantly including nickel in contact with the base metal, and a second plated metal layer predominantly including silver in contact with the first plated metal layer. The first plated metal layer has a first plated metal layer thickness of 0.1 to 5 microns, and the second plated metal layer has a second plated metal layer thickness of 0.2 to 5 microns. The semiconductor package further includes an adhesion promotion coating predominantly including silver oxide in contact with the second plated metal layer opposite the first plated metal layer, a semiconductor die mounted on the pad, a wire bond extending between the semiconductor die and a lead of the leads, and a mold compound covering the semiconductor die and the wire bond.

公开(公告)号：US09373572B2

公开(公告)日：2016-06-21

申请号：US14879622

申请日：2015-10-09

Applicant: Texas Instruments Incorporated

Inventor： Gregory E. Howard ,  Bernardo Gallegos ,  Rajiv Dunne ,  Darvin R. Edwards ,  Siva P. Gurrum ,  Manu J. Prakuzhy ,  Donald C. Abbott

IPC: H01L23/02 ,  H01L23/495 ,  H01L21/78 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49589 ,  H01L21/4821 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49109 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/13091 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/17724 ,  H01L2924/17747 ,  H01L2924/1776 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A packaged semiconductor device including a leadframe and a plurality of angularly shaped capacitors. The leadframe includes structures with surfaces and sidewalls. The angularly shaped capacitors are attached to surface portions of the leadframe structures. The angularly shaped capacitors have sidewalls coplanar with structure sidewalls. The angularly shaped capacitors includes a conductive material attached to the structure surface. The conductive material having pores covered by oxide and filled with conductive polymer. The angularly shaped capacitors topped by electrodes are made of a second metal.

Abstract translation: 一种封装半导体器件，包括引线框和多个角形电容器。 引线框架包括具有表面和侧壁的结构。 角形电容器附接到引线框结构的表面部分。 角形电容器具有与结构侧壁共面的侧壁。 角形电容器包括附着到结构表面的导电材料。 导电材料具有被氧化物覆盖并填充有导电聚合物的孔。 由电极顶起的角形电容器由第二金属制成。

公开(公告)号：US20150357238A1

公开(公告)日：2015-12-10

申请号：US14831163

申请日：2015-08-20

Applicant: Texas Instruments Incorporated

Inventor： Bernardo Gallegos ,  Abram Castro

IPC: H01L21/768 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L21/76858 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4871 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76885 ,  H01L23/3135 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02319 ,  H01L2224/03436 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/96 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Methods of fabricating integrated circuits are disclosed herein. A die having a side is provided. A conductive stud extends from the side in a direction that is substantially normal to the side. A first dielectric layer is affixed to the side of the die. The first dielectric layer has a first side and a second side. The first side of the first dielectric layer is affixed to the side of the die. The conductive stud pierces the first side of the first dielectric layer. A first via is formed through the first dielectric layer between the conductive stud and the second side. The first via is electrically connected to the conductive stud.

Abstract translation: 本文公开了制造集成电路的方法。 提供具有侧面的模具。 导电螺柱从基本上垂直于侧面的方向从侧面延伸。 第一电介质层固定在模具的侧面。 第一电介质层具有第一侧和第二侧。 第一介电层的第一侧固定在模具的侧面。 导电柱刺穿第一介电层的第一侧。 第一通孔在导电柱和第二侧之间通过第一电介质层形成。 第一通孔电连接到导电柱。

公开(公告)号：US09165873B1

公开(公告)日：2015-10-20

申请号：US14494916

申请日：2014-09-24

Applicant: Texas Instruments Incorporated

Inventor： Gregory E. Howard ,  Bernardo Gallegos ,  Rajiv Dunne ,  Darvin R. Edwards ,  Siva P. Gurrum ,  Manu J. Prakuzhy ,  Donald C. Abbott

IPC: H01L23/02 ,  H01L23/495

CPC classification number: H01L23/49589 ,  H01L21/4821 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49109 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/13091 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/17724 ,  H01L2924/17747 ,  H01L2924/1776 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A packaged semiconductor device including a leadframe made of a first metal, the leadframe including structures with surfaces and sidewalls; capacitors attached to surface portions of the leadframe structures, the capacitors having sidewalls coplanar with structure sidewalls; the capacitors including a foil of conductive material attached to the structure surface, the conductive material having pores covered by oxide and filled with conductive polymer, the capacitors topped by electrodes made of a second metal.

Abstract translation: 一种封装半导体器件，包括由第一金属制成的引线框架，所述引线框架包括具有表面和侧壁的结构; 电容器附接到引线框架结构的表面部分，电容器具有与结构侧壁共面的侧壁; 所述电容器包括附着到所述结构表面的导电材料箔，所述导电材料具有由氧化物覆盖并填充有导电聚合物的孔，所述电容器由由第二金属制成的电极顶起。

公开(公告)号：US20150115421A1

公开(公告)日：2015-04-30

申请号：US14064671

申请日：2013-10-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Bernardo Gallegos ,  Yong Lin

IPC: H01L23/495

CPC classification number: H01L23/49558 ,  H01L23/49541 ,  H01L23/49548 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and apparatus of minimizing resin bleed and mold flash on integrated lead finishes by providing groves on the external leads that can control the length of resin bleed.

Abstract translation: 通过在可以控制树脂流失长度的外部引线上提供树脂，使集成铅涂层上的树脂渗出和模具闪光最小化的方法和装置。

公开(公告)号：US11244881B2

公开(公告)日：2022-02-08

申请号：US16588544

申请日：2019-09-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Bernardo Gallegos

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/495

Abstract: A package comprises a molding and a conductive terminal in contact with the molding and having a first surface exposed to a first surface of the molding. The conductive terminal includes a cavity having a first portion extending along at least half of the first surface of the conductive terminal and a second portion extending along less than half of the first surface of the conductive terminal.

公开(公告)号：US09875930B2

公开(公告)日：2018-01-23

申请号：US14582349

申请日：2014-12-24

Applicant: Texas Instruments Incorporated

Inventor： Bernardo Gallegos ,  Abram Castro

IPC: H01L21/768 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L21/76838 ,  H01L21/56 ,  H01L21/76801 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/12105 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/9202 ,  H01L2924/15311 ,  H01L2224/13347 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Methods of packaging integrated circuits are disclosed herein. In one embodiment of a method. A die having a side is provided. A conductive stud is connected to the side of the die, wherein the conductive stud has a first end that is connected to the die and an opposite second end. The die is encapsulated except for the side. A first dielectric layer is affixed to the side of the die. The first dielectric layer has a first side and a second side. The first side of the first dielectric layer is affixed to the side of the die. The conductive stud enters the first side of the first dielectric layer. A conductive layer is affixed to the second side of the first dielectric layer. The second side of the conductive stud is affixed to the conductive layer using a conductive adhesive.

公开(公告)号：US09536781B2

公开(公告)日：2017-01-03

申请号：US14831163

申请日：2015-08-20

Applicant: Texas Instruments Incorporated

Inventor： Bernardo Gallegos ,  Abram Castro

IPC: H01L21/768 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/76858 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4871 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76885 ,  H01L23/3135 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02319 ,  H01L2224/03436 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/96 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Methods of fabricating integrated circuits are disclosed herein. A die having a side is provided. A conductive stud extends from the side in a direction that is substantially normal to the side. A first dielectric layer is affixed to the side of the die. The first dielectric layer has a first side and a second side. The first side of the first dielectric layer is affixed to the side of the die. The conductive stud pierces the first side of the first dielectric layer. A first via is formed through the first dielectric layer between the conductive stud and the second side. The first via is electrically connected to the conductive stud.

Abstract translation: 本文公开了制造集成电路的方法。 提供具有侧面的模具。 导电螺柱从基本上垂直于侧面的方向从侧面延伸。 第一电介质层固定在模具的侧面。 第一电介质层具有第一侧和第二侧。 第一介电层的第一侧固定在模具的侧面。 导电柱刺穿第一介电层的第一侧。 第一通孔在导电柱和第二侧之间通过第一电介质层形成。 第一通孔电连接到导电柱。