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    METHOD OF FABRICATING TRANSISTORS, INCLUDING AMBIENT OXIDIZING AFTER ETCHINGS INTO BARRIER LAYERS AND ANTI-REFLECTING COATINGS
    1.
    发明申请
    METHOD OF FABRICATING TRANSISTORS, INCLUDING AMBIENT OXIDIZING AFTER ETCHINGS INTO BARRIER LAYERS AND ANTI-REFLECTING COATINGS 审中-公开

    公开(公告)号：US20190304786A1

    公开(公告)日：2019-10-03

    申请号：US15944550

    申请日：2018-04-03

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Abbas ALI ,  Binghua HU ,  Stephanie L. HILBUN ,  Scott William JESSEN ,  Ronald CHIN ,  Jarvis Benjamin JACOBS

    IPC: H01L21/266 ,  H01L29/66

    Abstract: A method to fabricate a transistor comprises: forming a first dielectric layer on a semiconductor substrate; depositing a barrier layer on the first dielectric layer; depositing an anti-reflective coating on the barrier layer; depositing and exposing a pattern in a photoresist layer to radiation followed by etching to provide an opening; etching a portion of the anti-reflective coating below the opening; etching a portion of the barrier layer below the opening to expose a portion of the first dielectric layer; providing an ambient oxidizing agent to grow an oxide region followed by removing the barrier layer; implanting dopants into the semiconductor substrate after removing the barrier layer; removing the first dielectric layer after implanting dopants into the semiconductor substrate; and forming a second dielectric layer after removing the first dielectric layer, wherein the oxide region is grown to be thicker than the second dielectric layer.

    TWO-TRACK CROSS-CONNECT IN DOUBLE-PATTERNED STRUCTURE USING RECTANGULAR VIA
    2.
    发明申请
    TWO-TRACK CROSS-CONNECT IN DOUBLE-PATTERNED STRUCTURE USING RECTANGULAR VIA 审中-公开
    使用矩形横截面的双曲线结构中的双轨交叉连接

    公开(公告)号：US20140035160A1

    公开(公告)日：2014-02-06

    申请号：US14051078

    申请日：2013-10-10

    Applicant: Texas Instruments Incorporated

    Inventor： James Walter BLATCHFORD ,  Scott William JESSEN

    IPC: H01L23/48

    CPC classification number: H01L23/481 ,  H01L21/76816 ,  H01L21/76838 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An integrated circuit may be formed by forming a first interconnect pattern in a first plurality of parallel route tracks, and forming a second interconnect pattern in a second plurality of parallel route tracks, in which the second plurality of route tracks are alternated with the first plurality of route tracks. The first interconnect pattern includes a first lead pattern and the second interconnect pattern includes a second lead pattern, such that the route track containing the first lead pattern is immediately adjacent to the route track containing the second lead pattern. Metal interconnect lines are formed in the first interconnect pattern and the second interconnect pattern. A stretch crossconnect is formed in a vertical connecting level, such as a via or contact level, which electrically connects only the first lead and the second lead. The stretch crossconnect is formed concurrently with other vertical interconnect elements.

    Abstract translation: 可以通过在第一多个平行路径轨道中形成第一互连图案并且在第二多个平行路径轨道中形成第二互连图案来形成集成电路，其中第二多个路线轨道与第一多个平行路线轨道交替 的路线。 第一互连图案包括第一引线图案，并且第二互连图案包括第二引线图案，使得包含第一引线图案的路径轨道紧邻包含第二引线图案的路径轨迹。 金属互连线形成在第一互连图案和第二互连图案中。 拉伸交叉连接形成在仅连接第一引线和第二引线的垂直连接电平，例如通孔或接触电平。 拉伸交叉连接与其他垂直互连元件同时形成。

    METHODOLOGY OF FORMING CMOS GATES ON THE SECONDARY AXIS USING DOUBLE-PATTERNING TECHNIQUE
    5.
    发明申请
    METHODOLOGY OF FORMING CMOS GATES ON THE SECONDARY AXIS USING DOUBLE-PATTERNING TECHNIQUE 有权
    使用双模式技术在二次轴上形成CMOS栅的方法

    公开(公告)号：US20150170971A1

    公开(公告)日：2015-06-18

    申请号：US14563266

    申请日：2014-12-08

    Applicant: Texas Instruments Incorporated

    Inventor： Gregory Charles BALDWIN ,  Scott William JESSEN

    IPC: H01L21/8234 ,  H01L21/033

    CPC classification number: H01L21/823456 ,  H01L21/0274 ,  H01L21/32139 ,  H01L21/823412 ,  H01L21/823462 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823857 ,  H01L27/0207

    Abstract: An integrated circuit containing core transistors and I/O transistors oriented perpendicular to the core transistors is formed by exposing a gate etch mask layer stack through a gate pattern photomask including core transistor gates and oversized I/O transistor gates. Core transistor gate lengths are defined by the gate pattern photomask. A first gate hardmask etch process removes the gate hardmask layer in exposed areas. The process continues with exposing a gate trim mask layer stack through a gate trim photomask. I/O gate lengths are defined by the gate trim photomask. A second gate hardmask etch process removes the gate hardmask layer in exposed areas. A gate etch operation removes polysilicon exposed by the gate hardmask layer to form gates for the core transistors and I/O transistors. The integrated circuit may also include I/O transistors oriented parallel to the core transistors, with gate lengths defined by the gate pattern photomask.

    Abstract translation: 包含核心晶体管和垂直于核心晶体管的I / O晶体管的集成电路通过通过包括核心晶体管栅极和超大I / O晶体管栅极的栅极图案光掩模曝光栅极蚀刻掩模层堆叠来形成。 核心晶体管栅极长度由栅极图案光掩模限定。 第一栅极硬掩模蚀刻工艺去除暴露区域中的栅极硬掩模层。 该过程继续通过栅极修整光掩模曝光栅极微调掩模层堆叠。 I / O栅极长度由栅极修整光掩模定义。 第二栅极硬掩模蚀刻工艺去除暴露区域中的栅极硬掩模层。 栅极蚀刻操作去除由栅极硬掩模层暴露的多晶硅，以形成核心晶体管和I / O晶体管的栅极。 集成电路还可以包括与核心晶体管平行取向的I / O晶体管，栅极长度由栅极图案光掩模限定。

    ELONGATED CONTACTS USING LITHO-FREEZE-LITHO-ETCH PROCESS
    7.
    发明申请
    ELONGATED CONTACTS USING LITHO-FREEZE-LITHO-ETCH PROCESS 有权
    使用LITHO-FREEZE-LITHO-ETCH工艺的连接接头

    公开(公告)号：US20150170975A1

    公开(公告)日：2015-06-18

    申请号：US14572891

    申请日：2014-12-17

    Applicant: Texas Instruments Incorporated

    Inventor： James Walter BLATCHFORD ,  Scott William JESSEN

    IPC: H01L21/8238 ,  H01L21/027 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/3213

    CPC classification number: H01L21/823475 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/762 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76895 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/0207

    Abstract: A process of forming an integrated circuit containing elongated contacts which connect to three active areas and/or MOS gates, and elongated contacts which connect to two active areas and/or MOS gates and directly connect to a first level interconnect, using a litho-freeze-litho-etch process for a contact etch mask. A process of forming an integrated circuit containing elongated contacts which connect to three active areas and/or MOS gates, and elongated contacts which connect to two active areas and/or MOS gates and directly connect to a first level interconnect, using a litho-freeze-litho-etch process for a first level interconnect trench etch mask. A process of forming the integrated circuit using a litho-freeze-litho-etch process for a contact etch mask and a litho-freeze-litho-etch process for a first level interconnect trench etch mask.

    Abstract translation: 一种形成集成电路的过程，该集成电路包含连接到三个有源区和/或MOS栅的细长触点，以及使用光刻冻结连接到两个有源区和/或MOS栅并直接连接到第一级互连的细长触点 用于接触蚀刻掩模的光蚀刻工艺。 一种形成集成电路的过程，该集成电路包含连接到三个有源区和/或MOS栅的细长触点，以及使用光刻冻结连接到两个有源区和/或MOS栅并直接连接到第一级互连的细长触点 用于第一级互连沟槽蚀刻掩模的光蚀刻工艺。 使用用于接触蚀刻掩模的光刻冷冻 - 光刻蚀工艺和用于第一级互连沟槽蚀刻掩模的光刻冷冻 - 光刻蚀工艺形成集成电路的工艺。

    METHODS FOR ETCHING METAL INTERCONNECT LAYERS
    10.
    发明申请
    METHODS FOR ETCHING METAL INTERCONNECT LAYERS 审中-公开

    公开(公告)号：US20200328149A1

    公开(公告)日：2020-10-15

    申请号：US16383176

    申请日：2019-04-12

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Poornika FERNANDES ,  Bhaskar SRINIVASAN ,  Scott William JESSEN ,  Guruvayurappan S. MATHUR

    IPC: H01L23/522 ,  H01L49/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/02

    Abstract: In some examples, a method comprises: obtaining a substrate having at a metal interconnect layer deposited over the substrate; forming a first dielectric layer on the metal interconnect layer; forming a second dielectric layer on the first dielectric layer; forming a capacitor metal layer on the second dielectric layer; patterning and etching the capacitor metal layer and the second dielectric layer to the first dielectric layer to leave a portion of the capacitor metal layer and the second dielectric layer on the first dielectric layer; forming an anti-reflective coating to cover the portion of the capacitor metal layer and the second dielectric layer, and to cover the metal interconnect layer; and patterning the metal interconnect layer to form a first metal layer and a second metal layer.

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