公开(公告)号：US20230352576A1

公开(公告)日：2023-11-02

申请号：US17876572

申请日：2022-07-29

Applicant: University of Electronic Science and Technology of China ,  Institute of Electronic and Information Engineering of UESTC in Guangdong

Inventor： Ming QIAO ,  Ruidi WANG ,  Yibing WANG ,  Bo ZHANG

IPC: H01L29/40 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/7811 ,  H01L29/0634 ,  H01L29/405

Abstract: A termination structure of a super-junction power device has a novel polysilicon resistive field plate at the top of a termination region between a transition region and an edge of the device. By utilizing the regular distribution of potential in the field plate, an additional electric field is introduced at the top of the termination structure to limit the expansion of a non-depletion region and optimize the distribution of charges. The termination structure includes a first doping type epitaxial layer, a second doping type compensation region, a second doping type body region, a second doping type lateral connection layer, a second doping type body contact region, a first doping type source contact region, a gate oxide layer, a passivation layer, a field oxide layer, a gate electrode, a second doping type edge contact region, a polysilicon resistive field plate, a metal layer and the like.

公开(公告)号：US20230170411A1

公开(公告)日：2023-06-01

申请号：US17714176

申请日：2022-04-06

Applicant: University of Electronic Science and Technology of China

Inventor： Ming QIAO ,  Yong CHEN ,  Wenliang LIU ,  Dong FANG ,  Fabei ZHANG ,  Bo ZHANG

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L21/265 ,  H01L21/266 ,  H01L21/761 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/063 ,  H01L29/1095 ,  H01L29/407 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/761 ,  H01L29/66734

Abstract: A bidirectional conduction trench gate power MOS device and a manufacturing method thereof are provided. A gate electrode, a source electrode and a drain electrode are formed on a surface of a silicon wafer to realize a bidirectional conduction and bidirectional blocking power MOS device used in an application environment such as lithium battery BMS protection. A device structure of the bidirectional conduction trench gate power MOS device has advantages compared with double-transistor series connection used in a conventional BMS and other structures for realizing a bidirectional conduction: firstly, the bidirectional conduction trench gate power MOS device needs to occupy half or less area compared with a conventional mode, improving a degree of integration; secondly, the device structure has a simple manufacturing process and a low manufacturing cost reducing manufacturing problems; thirdly, the drain electrode and the source electrode of the device structure are exchanged to realize a symmetrical structure.

公开(公告)号：US20230129440A1

公开(公告)日：2023-04-27

申请号：US17831454

申请日：2022-06-03

Applicant: University of Electronic Science and Technology of China ,  Institute of Electronic and Information Engineering of UESTC in Guangdong

Inventor： Ming QIAO ,  Ruidi WANG ,  Yibing WANG ,  Wenyang BAI ,  Bo ZHANG

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L21/265 ,  H01L21/266 ,  H01L21/761 ,  H01L29/66

Abstract: A method for manufacturing a semiconductor device is provided. A drift region and a compensation region are formed through a deep trench etching and a filling technology. A plurality of modulation doping regions are formed at a top of the drift region by an epitaxy and an ion implantation. A modulation region is introduced, wherein the modulation region flexibly modifies capacitance characteristics and achieve improved dynamic characteristics.

公开(公告)号：US20230053369A1

公开(公告)日：2023-02-23

申请号：US17744779

申请日：2022-05-16

Applicant: University of Electronic Science and Technology of China

Inventor： Wentong ZHANG ,  Ning TANG ,  Ke ZHANG ,  Nailong HE ,  Ming QIAO ,  Zhaoji LI ,  Bo ZHANG

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/739 ,  H01L29/66 ,  H01L29/78

Abstract: An SOI lateral homogenization field high voltage power semiconductor device, and a manufacturing method and application thereof are provided. The device includes a type I conductive semiconductor substrate, a type II conductive drift region, a type I field clamped layer, type I and type II conductive well regions, the first dielectric oxide layer forming a field oxide layer, the second dielectric oxide layer forming a gate oxide layer, a type II conductive buried dielectric layer, a type II conductive source heavily doped region, a type II conductive drain heavily doped region. The first dielectric oxide layer and the floating field plate polysilicon electrodes form a vertical floating field plate distributed throughout the type II conductive drift region to form a vertical floating equipotential field plate array. When the device is in on-state, high doping concentration can be realized by the full-region depletion effect form the vertical field plate arrays.

公开(公告)号：US20200066714A1

公开(公告)日：2020-02-27

申请号：US16255851

申请日：2019-01-24

Applicant: University of Electronic Science and Technology of China

Inventor： Ming QIAO ,  Song PU ,  Bo ZHANG

IPC: H01L27/06 ,  H01L21/784 ,  H01L21/8258

Abstract: A BIPOLAR-CMOS-DMOS (BCD) semiconductor device and manufacturing method, which can integrate a Junction Field-Effect Transistor (JFET), two classes of Vertical Double-diffusion Metal Oxide Semiconductor (VDMOS), a Lateral Insulated-Gate Bipolar Transistor (LIGBT) and seven kinds of Laterally Diffused Metal Oxide Semiconductor (LDMOS), a low-voltage Negative channel Metal Oxide Semiconductor (NMOS), a low-voltage Positive channel Metal Oxide Semiconductor (PMOS), a low-voltage Negative-Positive-Negative (NPN) transistor and a low-voltage Positive-Negative-Positive (PNP) transistor, and a diode in the same chip. Bipolar devices in the analog circuit, power components in the switch circuit, Complementary Metal Oxide Semiconductor (CMOS) devices in the logic circuit and other kinds of lateral and vertical components are integrated. This present invention saves costs at the same time greatly improve chip integration. The manufacturing method of the present invention is simple, and the difficulty of process is relatively less.

公开(公告)号：US20190326679A1

公开(公告)日：2019-10-24

申请号：US16386296

申请日：2019-04-17

Applicant: University of Electronic Science and Technology of China

Inventor： Yujian CHENG ,  Yafei WU ,  Jinfan ZHANG ,  Fan ZHAO ,  Chunxu BAI ,  Yong FAN ,  Kaijun SONG ,  Bo ZHANG ,  Xianqi LIN ,  Yonghong ZHANG

IPC: H01Q13/22 ,  H01Q21/06 ,  H01Q1/50 ,  H01P3/08 ,  H01P3/12 ,  H01P5/08 ,  H01Q1/38

Abstract: A slot array antenna including a smooth curved surface and planar feed structures which are respectively disposed at two ends of the smooth curved surface and are tangent to the smooth curved surface. The smooth curved surface includes at least two arcs mutually connected by smooth transition. The at least two arcs each includes an upper copper metal layer, a lower copper metal layer, and a dielectric substrate layer between the upper and lower copper metal layers. The upper copper metal layer includes radiating slots, and the adjacent radiating slots in a linear array have opposite offsets along the center line of the slot array antenna. The dielectric substrate layer includes metallic vias symmetrically arranged on both sides of the central line of the antenna to form a substrate integrated waveguide.

公开(公告)号：US20190237576A1

公开(公告)日：2019-08-01

申请号：US15955706

申请日：2018-04-18

Applicant: University of Electronic Science and Technology of China

Inventor： Ming QIAO ,  Zhengkang WANG ,  Ruidi WANG ,  Zhao QI ,  Bo ZHANG

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/40 ,  H01L29/08

CPC classification number: H01L29/7813 ,  H01L29/063 ,  H01L29/0649 ,  H01L29/0852 ,  H01L29/402 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/7825 ,  H01L29/7833

Abstract: A power semiconductor device including a first conductivity type semiconductor substrate, a drain metal electrode, a first conductivity type semiconductor drift region, and a second conductivity type semiconductor body region. The second conductivity type semiconductor body region includes a first conductivity type semiconductor source region and anti-punch-through structure; the anti-punch-through structure is a second conductivity type semiconductor body contact region or metal structure; the lower surface of the anti-punch-through structure coincides with the upper surface of the first conductivity type semiconductor drift region or the distance between the two is less than 0.5 μm, so that make the device avoid from punch-through. An anti-punch-through structure is introduced at the source end of the device to avoid punch-through breakdown caused by short channel and light-doped body region.

公开(公告)号：US20180158936A1

公开(公告)日：2018-06-07

申请号：US15695078

申请日：2017-09-05

Applicant: University of Electronic Science and Technology of China

Inventor： Wanjun CHEN ,  Yijun SHI ,  Jie LIU ,  Xingtao CUI ,  Guanhao HU ,  Chao LIU ,  Qi ZHOU ,  Bo ZHANG

IPC: H01L29/739 ,  H01L29/20 ,  H01L29/205

Abstract: The present invention relates to the field of semiconductor switches, and relates more particularly to a GaN-based bidirectional switch device. The present invention provides a gate-controlled tunneling bidirectional switch device without Ohmic-contact, which avoids a series of negative effects (such as current collapse, incompatibility with traditional CMOS process) caused by the high temperature ohm annealing process. Each insulated gate structure near schottky-contact controls the band structure of the schottky-contact to change the working state of the device, realizing the bidirectional switch's ability of bidirectional conducting and blocking. Due to the only presence of schottky in this invention, no heavy elements such as gold is needed, and this device is compatible with traditional CMOS technology.

公开(公告)号：US20160315142A1

公开(公告)日：2016-10-27

申请号：US15197701

申请日：2016-06-29

Applicant: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA ,  ELECTRONIC AND INFORMATION ENGINEERING IN DONGGUAN , UESTC

Inventor： Zehong LI ,  Wenlong SONG ,  Xunyi SONG ,  Hongming GU ,  Youbiao ZOU ,  Jinping ZHANG ,  Bo ZHANG

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/0634 ,  H01L21/263 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802

Abstract: A method for manufacturing a vertical super junction drift layer of a power semiconductor device. The method includes: a): adopting P+ single crystal silicon to prepare a P+ substrate; b): finishing top processes of the devices on the P+ substrate, forming at least P type region, manufacturing active area and metallizing the top surface of the P+ substrate; c): thinning the back surface of the P+ single crystal silicon; d): selectively implanting H+ ions at the back surface repeatedly and then annealing to form N pillars in the P type region; and e): metallizing the back surface.

Abstract translation: 一种用于制造功率半导体器件的垂直超结漂移层的方法。 该方法包括：a）：采用P +单晶硅制备P +底物; b）：完成P +衬底上的器件的顶部工艺，至少形成P型区域，制造有源面积并金属化P +衬底的顶表面; c）：使P +单晶硅的背面变薄; d）：重复地在背面注入H +离子，然后退火以在P型区域中形成N柱; 和e）：金属化背面。

公开(公告)号：US20240112914A1

公开(公告)日：2024-04-04

申请号：US18121609

申请日：2023-03-15

Applicant: University of Electronic Science and Technology of China

Inventor： Bo ZHANG ,  Teng LIU ,  Wentong ZHANG ,  Nailong HE ,  Sen ZHANG ,  Ming QIAO ,  Zhaoji LI

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/027 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213

CPC classification number: H01L21/0337 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32055 ,  H01L21/32137 ,  H01L21/32139

Abstract: A new variable selective etching technology for thick SOI devices. An SOI material is etched by the following steps: (1) providing an SOI wafer; (2) depositing a composite hard mask with a variable selection ratio to replace a traditional hard mask with an invariable selection ratio; (3) applying a photoresist; (4) mask making, namely defining a to-be-etched region by using a photoetching plate; (5) etching the photoresist in the defined region; (6) etching the composite hard mask; (7) removing the photoresist; (8) etching top silicon by using a second etching method at a first selection ratio; and (9) etching a buried oxide layer by using a third etching method at a second selection ratio. The new variable selective etching technology avoids the damage to a side wall of a deep trench when the buried oxide layer is etched, and does not need to use an excessive thick hard mask.