公开(公告)号：US4672738A

公开(公告)日：1987-06-16

申请号：US776161

申请日：1985-09-13

Applicant: Reinhard Stengl ,  Ulrich Goesele ,  Christine Fellinger

Inventor： Reinhard Stengl ,  Ulrich Goesele ,  Christine Fellinger

IPC: H01L21/033 ,  H01L21/22 ,  H01L21/265 ,  H01L21/266 ,  H01L29/06 ,  H01L29/74

CPC classification number: H01L21/0334 ,  H01L21/266 ,  H01L29/0615 ,  H01L29/0688 ,  Y10S148/01 ,  Y10S438/965

Abstract: A method for the manufacture of a pn junction having a high breakdown voltage at the boundary surface of a semiconductor body, utilizing a mask which has a relatively large opening for introducing a dopant therethrough into the semiconductor body, the mask having a marginal edge which extends laterally beyond the edge of the relatively large opening. In the marginal edge, the mask is provided with smaller, auxiliary openings, the openings being sized and spaced such that lesser amounts of dopant pass through the opening as the distance of the auxiliary openings from the edge of the relatively larger opening increases. Upon introducing the dopant into the semiconductor body through the mask, there is generated a doping profile which gradually approaches the boundary surface with increasing distance from the edge of the relatively large opening.

Abstract translation: 一种用于制造在半导体本体的边界表面具有高击穿电压的pn结的方法，利用具有相对较大的开口的掩模，用于将掺杂剂引入到半导体本体中，所述掩模具有延伸的边缘 横向超过相对较大开口的边缘。 在边缘处，掩模设置有较小的辅助开口，开口的尺寸和间隔使得当辅助开口距相对较大开口的边缘的距离增加时，较少量的掺杂剂通过开口。 当通过掩模将掺杂剂引入半导体本体时，产生掺杂分布，其随着距离相对大的开口的边缘的距离增加而逐渐接近边界表面。

公开(公告)号：US4907056A

公开(公告)日：1990-03-06

申请号：US248150

申请日：1988-09-23

Applicant: Ulrich Goesele ,  Reinhard Stengl

Inventor： Ulrich Goesele ,  Reinhard Stengl

IPC: H01L29/06 ,  H01L29/74 ,  H01L29/861

CPC classification number: H01L29/0615 ,  H01L29/7424

Abstract: A semiconductor region that is inserted into a semiconductor member is provided, the latter being separated from the former by a planar pn junction including a first, more highly doped sub-region and a second, more lightly doped sub-region that is limited by a part of the pn junction that gradually approaches a boundary surface of the semiconductor member. An electrode contacts the semiconductor region and covers a part of the second sub-region and extends toward the lateral limitation of the semiconductor region to such an extent that, given the application of a voltage inhibiting the pn junction the space charge zone forming thereat has its edge lying in the boundary surface just reaching the electrode edge given a reduced breakdown voltage.

Abstract translation: 设置插入到半导体部件中的半导体区域，后者通过平面pn结与前者分离，该平面pn结包括第一，更高掺杂的子区和第二，更轻掺杂的子区，该子区被 pn结的部分逐渐接近半导体部件的边界面。 电极接触半导体区域并且覆盖第二子区域的一部分并且朝向半导体区域的横向限制延伸到这样的程度，即，在施加抑制pn结的电压的情况下，在其上形成的空间电荷区域具有其 边缘位于刚刚到达电极边缘的边界表面，给出了降低的击穿电压。

公开(公告)号：US20090011556A9

公开(公告)日：2009-01-08

申请号：US09948010

申请日：2001-09-05

Applicant: Gerhard Beitel ,  Wolfgang Hoenlein ,  Reinhard Stengl ,  Elke Fritsch ,  Siegfried Schwarzl ,  Hermann Wendt

Inventor： Gerhard Beitel ,  Wolfgang Hoenlein ,  Reinhard Stengl ,  Elke Fritsch ,  Siegfried Schwarzl ,  Hermann Wendt

IPC: H01L21/00 ,  H01L21/8242

CPC classification number: H01L28/60 ,  H01L21/02071 ,  H01L21/32136 ,  H01L28/55

Abstract: A method for producing a microelectronic structure is suggested in which a layer structure (30) which partially covers a substrate (5) and which comprises at least one first conductive layer (15,20) which reaches to a side wall (35) of the layer structure (30), is covered with a second conductive layer (45). The second conductive layer (45) is then subsequently back-etched to as great an extent as possible with an etching process with physical delamination, wherein delaminated material deposits on the side wall (35) of the layer structure (30). On the side wall (35) the delaminated material forms a protection layer (60) by means of which the first conductive layer (15,20) is to be protected from attack by oxygen to the furthest extent possible.

公开(公告)号：US07420228B2

公开(公告)日：2008-09-02

申请号：US11246420

申请日：2005-10-07

Applicant: Josef Bock ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schafer

Inventor： Josef Bock ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schafer

IPC: H01L29/739

CPC classification number: H01L29/66287 ,  H01L29/0821 ,  H01L29/167 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

Abstract: A bipolar transistor comprising a collector region of a first conduction type, and a subcollector region of the first conduction type at a first side of the collector region. The transistor further includes a base region of the second conduction type provided at a second side of the collector region, and an emitter region of the first conduction type which is provided above the base region on the side remote from the collection region. A carbon-doped semiconductor region is provided on the first side alongside the collector region. The bipolar transistor is characterized in that the carbon-doped semiconductor region has a carbon concentration of 1019-1021 cm−3 and the base region has a smaller cross section than the collector region and the collector region has, in the overlap region with the base region, a region having an increased doping compared with the remaining region. The carbon-doped semiconductor region prevents an outdiffusion from the zone of the collector region into the remaining region of the collector region.

Abstract translation: 包括第一导电类型的集电极区域和在集电极区域的第一侧的第一导电类型的子集电极区域的双极晶体管。 晶体管还包括设置在集电极区域的第二侧的第二导电类型的基极区域和设置在远离收集区域的一侧的基极区域上方的第一导电类型的发射极区域。 在集电极区域旁边的第一侧设置碳掺杂半导体区域。 双极晶体管的特征在于，碳掺杂半导体区域的碳浓度为10〜20±0.01cm -3，基极 区域具有比集电极区域更小的横截面，并且在与基极区域的重叠区域中具有与剩余区域相比具有增加的掺杂的区域。 碳掺杂半导体区域防止从集电极区域向集电极区域的剩余区域的扩散。

公开(公告)号：US06995416B2

公开(公告)日：2006-02-07

申请号：US10853734

申请日：2004-05-26

Applicant: Hans Reisinger ,  Reinhard Stengl ,  Herbert Schäfer

Inventor： Hans Reisinger ,  Reinhard Stengl ,  Herbert Schäfer

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: G11C13/025 ,  B82Y10/00 ,  G11C13/0033 ,  H01L27/10814 ,  H01L27/10852 ,  H01L28/91 ,  H01L51/0048 ,  H01L51/0052 ,  Y10S977/842 ,  Y10S977/943

Abstract: The invention provides a memory device for storing electrical charge, which has, as memory elements, tube elements applied on an electrode layer and connect-connected thereto. The tube elements are provided with a dielectric coating, a filling material for filling the space between the tube elements being provided. A counter-electrode connected to the filling material is formed such that an electrical capacitor for storing electrical charge is formed between the electrode layer and the counter-electrode. The tube elements advantageously comprise carbon nanotubes, as a result of which the capacitance of the capacitor on account of a drastic increase in the area of the capacitor electrode surface.

Abstract translation: 本发明提供一种用于存储电荷的存储装置，其具有作为存储元件的施加在电极层上并连接到其上的管元件。 管元件设置有电介质涂层，用于填充管元件之间的空间的填充材料。 与填充材料连接的对电极形成为在电极层和对电极之间形成用于存储电荷的电容器。 管元件有利地包括碳纳米管，结果由于电容器电极表面的面积急剧增加，电容器的电容。

公开(公告)号：US20050006723A1

公开(公告)日：2005-01-13

申请号：US10912344

申请日：2004-08-04

Applicant: Reinhard Stengl ,  Thomas Meister ,  Herbert Schafer ,  Martin Franosch

Inventor： Reinhard Stengl ,  Thomas Meister ,  Herbert Schafer ,  Martin Franosch

IPC: H01L21/331 ,  H01L29/732 ,  H01L31/0328

CPC classification number: H01L29/66287 ,  H01L29/7322

Abstract: A bipolar transistor includes a first layer with a collector. A second layer has a base cutout for a base. A third layer includes a lead for the base. The third layer is formed with an emitter cutout for an emitter. An undercut is formed in the second layer adjoining the base cutout. The base is at least partially located in the undercut. In order to obtain a low transition resistance between the lead and the base, an intermediate layer is provided between the first and the second layer. The intermediate layer is selectively etchable with respect to the second layer. At least in the region of the undercut between the lead and the base, a base connection zone is provided that can be adjusted independent of other production conditions. The intermediate layer is removed in a contact region with the base.

Abstract translation: 双极晶体管包括具有集电极的第一层。 第二层具有用于基座的基部切口。 第三层包括用于底座的引线。 第三层形成有用于发射极的发射极切口。 在与基座切口相邻的第二层中形成底切。 基部至少部分位于底切中。 为了在引线和基底之间获得低的过渡电阻，在第一和第二层之间设置中间层。 中间层相对于第二层可选择性地蚀刻。 至少在引线和基座之间的底切区域中，提供可以独立于其他生产条件进行调节的基础连接区域。 在与基底的接触区域中去除中间层。

公开(公告)号：US6165835A

公开(公告)日：2000-12-26

申请号：US341937

申请日：1999-07-20

Applicant: Hermann Wendt ,  Hans Reisinger ,  Andreas Spitzer ,  Reinhard Stengl ,  Ulrike Gruning ,  Josef Willer ,  Wolfgang Honlein ,  Volker Lehmann

Inventor： Hermann Wendt ,  Hans Reisinger ,  Andreas Spitzer ,  Reinhard Stengl ,  Ulrike Gruning ,  Josef Willer ,  Wolfgang Honlein ,  Volker Lehmann

IPC: H01L27/04 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8242 ,  H01L29/94

CPC classification number: H01L27/10861 ,  H01L29/66181 ,  Y10S438/96

Abstract: In producing a silicon capacitor, hole structures (2) are created in a silicon substrate (1), at the surface of which structures a conductive zone (3) is created by doping and whose surface is provided with a dielectric layer (4) and a conductive layer (5), without filling the hole structures (2). To compensate mechanical strains upon the silicon substrate (1) which are effected by the doping of the conductive zone (3), a conformal auxiliary layer (6) is formed on the surface of the conductive layer (5), which auxiliary layer is under a compressive mechanical stress.

Abstract translation: PCT No.PCT / DE98 / 00089 Sec。 371日期1999年7月20日 102（e）1999年7月20日PCT 1998年1月12日PCT PCT。 出版物WO98 / 32166 日期1998年7月23日在制造硅电容器中，在硅衬底（1）中形成孔结构（2），其表面通过掺杂形成导电区（3），并且其表面设置有电介质 层（4）和导电层（5），而不填充孔结构（2）。 为了补偿通过掺杂导电区（3）实现的硅衬底（1）上的机械应变，在导电层（5）的表面上形成共形辅助层（6），该辅助层在下面 压缩机械应力。

公开(公告)号：US5973385A

公开(公告)日：1999-10-26

申请号：US736301

申请日：1996-10-24

Applicant: Jeffrey Peter Gambino ,  Son Van Nguyen ,  Reinhard Stengl

Inventor： Jeffrey Peter Gambino ,  Son Van Nguyen ,  Reinhard Stengl

IPC: H01L21/28 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/58

CPC classification number: H01L21/02164 ,  H01L21/02129 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/31612 ,  H01L21/76801 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10T428/24926

Abstract: Significant amounts of pattern distortion were found to be the result of reflowing borophosphosilicate glass (BPSG) and silicon dioxide shrinkage during high temperature junction anneals. In order to remedy this problem, a method for suppressing the pattern distortion by subjecting the wafer coated with BPSG and with silicon dioxide layers to a high temperature anneal before patterning is disclosed. The high temperature anneal densifies the undoped silicon dioxide before patterning, so that shrinkage of the undoped silicon dioxide does not affect the patterning steps.

公开(公告)号：US5827765A

公开(公告)日：1998-10-27

申请号：US605622

申请日：1996-02-22

Applicant: Reinhard Stengl ,  Erwin Hammerl ,  Herbert L. Ho ,  Jack A. Mandelman ,  Radhika Srinivasan ,  Alvin P. Short

Inventor： Reinhard Stengl ,  Erwin Hammerl ,  Herbert L. Ho ,  Jack A. Mandelman ,  Radhika Srinivasan ,  Alvin P. Short

IPC: H01L27/00 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  H01L21/20

CPC classification number: H01L27/10861 ,  H01L27/10832

Abstract: A method for making an electrical connection between a trench storage capacitor and an access transistor in a DRAM cell. The electrical connection is formed through the selectively controlled outdiffusion of either N-type or P-type dopants present in the trench through a single crystalline semiconducting material which is grown by epitaxy (epi) from the trench sidewall. This epitaxially grown single crystalline layer acts as a barrier to excessive dopant outdiffusion which can occur in the processing of conventional DRAMs.

Abstract translation: 一种用于在DRAM单元中的沟槽存储电容器和存取晶体管之间进行电连接的方法。 电连接是通过选择性地控制存在于沟槽中的N型或P型掺杂剂的扩散形成的，该单晶通过从沟槽侧壁外延（epi）生长的单晶半导体材料。 该外延生长的单晶层作为在常规DRAM的处理中可能发生的过量掺杂剂扩散扩散的障碍。

公开(公告)号：US5449310A

公开(公告)日：1995-09-12

申请号：US222597

申请日：1994-04-04

Applicant: Reinhard Stengl ,  Wolfgang Hoenlein

Inventor： Reinhard Stengl ,  Wolfgang Hoenlein

IPC: H01J1/304 ,  H01J9/02 ,  H01J21/10 ,  H01J1/30

CPC classification number: H01J1/3042 ,  H01J21/105 ,  H01J9/025 ,  H01J2201/30403 ,  H01J2201/30407

Abstract: Rod-shaped or cylindrical structures in the nm range on a substrate of silicon are manufactured. A first cylinder of silicon is selectively epitaxially deposited in the hole of a mask layer of oxide, and the mask layer is removed. The silicon is then oxidized to form an oxide layer having such a thickness that a thinner, second cylinder of silicon having practically the same height as the first cylinder remains. In a last step, this oxide layer is removed, so that the second cylinder forms a freestanding silicon rod on the surface of the substrate.

Abstract translation: 制造在硅衬底上的nm范围内的棒状或圆柱形结构。 硅的第一圆柱体被选择性地外延沉积在氧化物的掩模层的孔中，并且去除掩模层。 然后将硅氧化以形成具有这样厚度的氧化物层，使得具有与第一气缸几乎具有相同高度的较薄的第二硅柱体保持不变。 在最后一步中，去除该氧化物层，使得第二圆柱体在基底表面上形成独立的硅棒。