公开(公告)号：US20070040261A1

公开(公告)日：2007-02-22

申请号：US11466279

申请日：2006-08-22

申请人： Wolfgang Hetzel ,  Jochen Thomas ,  Peter Weitz ,  Ingo Wennemuth

发明人： Wolfgang Hetzel ,  Jochen Thomas ,  Peter Weitz ,  Ingo Wennemuth

IPC分类号： H01L23/02

CPC分类号： H01L23/3128 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor component (10) has an interposer substrate (1) as stack element of a semiconductor component stack (25). The interposer substrate (1) has, on one of the interposer substrate sides (2, 4), a semiconductor chip protected by plastics composition (12) in its side edges (22). An interposer structure (3) partly covered by a plastics composition (12) is arranged on the interposer side (2, 4) opposite to the semiconductor chip (6). Edge regions (11) of the interposer substrate (1) remain free of any plastics composition (12) and have, on both interposer sides (2, 4) external contact pads (7) which are electrically connected to one another via through contacts (8).

摘要翻译： 半导体部件（10）具有作为半导体部件堆叠（25）的堆叠元件的插入基板（1）。 所述插入器基板（1）在所述插入器基板侧（2,4）中的一个上具有在其侧边缘（22）中被塑料组合物（12）保护的半导体芯片。 在与半导体芯片（6）相对的插入器侧（2,4）上布置有由塑料组合物（12）部分覆盖的插入器结构（3）。 插入器基板（1）的边缘区域（11）保持不含任何塑料组合物（12），并且在两个插入件侧（2,4）上通过接触件彼此电连接的外部接触焊盘（7） 8）。

公开(公告)号：US08624372B2

公开(公告)日：2014-01-07

申请号：US11466279

申请日：2006-08-22

申请人： Wolfgang Hetzel ,  Jochen Thomas ,  Peter Weitz ,  Ingo Wennemuth

发明人： Wolfgang Hetzel ,  Jochen Thomas ,  Peter Weitz ,  Ingo Wennemuth

IPC分类号： H01L23/02

CPC分类号： H01L23/3128 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor component (10) has an interposer substrate (1) as stack element of a semiconductor component stack (25). The interposer substrate (1) has, on one of the interposer substrate sides (2, 4), a semiconductor chip protected by plastics composition (12) in its side edges (22). An interposer structure (3) partly covered by a plastics composition (12) is arranged on the interposer side (2, 4) opposite to the semiconductor chip (6). Edge regions (11) of the interposer substrate (1) remain free of any plastics composition (12) and have, on both interposer sides (2, 4) external contact pads (7) which are electrically connected to one another via through contacts (8).

摘要翻译： 半导体部件（10）具有作为半导体部件堆叠（25）的堆叠元件的插入基板（1）。 所述插入器基板（1）在所述插入器基板侧（2,4）中的一个上具有在其侧边缘（22）中被塑料组合物（12）保护的半导体芯片。 在与半导体芯片（6）相对的插入器侧（2,4）上布置有由塑料组合物（12）部分覆盖的插入件结构（3）。 插入器基板（1）的边缘区域（11）保持不含任何塑料组合物（12），并且在两个插入件侧（2,4）上通过接触件彼此电连接的外部接触焊盘（7） 8）。

公开(公告)号：US07198979B2

公开(公告)日：2007-04-03

申请号：US10701742

申请日：2003-11-04

申请人： Jochen Thomas ,  Wolfgang Hetzel ,  Ingo Wennemuth

发明人： Jochen Thomas ,  Wolfgang Hetzel ,  Ingo Wennemuth

IPC分类号： H01L21/00 ,  H01L21/46 ,  H01L21/44 ,  H01L23/02 ,  H01L29/40

CPC分类号： H01L23/3157 ,  H01L23/3128 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of stacking semiconductor chips includes providing four semiconductor chips that each include a top surface with central bond pads. Each of the bond pads is electrically coupled to second bond pads located in a peripheral portion of the semiconductor chip through a conductive layer. The first and the second semiconductor chips are arranged alongside one another on a carrier substrate. The second bond pads from the first and second semiconductor chips are bonded to corresponding landing pads on the substrate. The third semiconductor chip is then stacked over the first semiconductor chip and the fourth semiconductor chip over the second semiconductor chip. The second bond pads of the third and fourth semiconductor chips can then be bonded to contact pads of the substrate. The substrate can then be separated into a first stack that includes the first and third semiconductor chips and a second stack that includes the second and fourth semiconductor chips.

摘要翻译： 堆叠半导体芯片的方法包括提供四个半导体芯片，每个半导体芯片包括具有中心焊盘的顶表面。 每个接合焊盘通过导电层电耦合到位于半导体芯片的周边部分中的第二接合焊盘。 第一和第二半导体芯片彼此并排地布置在载体衬底上。 来自第一和第二半导体芯片的第二接合焊盘被结合到衬底上的相应的着陆焊盘。 然后将第三半导体芯片堆叠在第二半导体芯片上方的第一半导体芯片和第四半导体芯片上。 然后可以将第三和第四半导体芯片的第二接合焊盘接合到衬底的接触焊盘。 然后可以将衬底分离成包括第一和第三半导体芯片的第一堆叠以及包括第二和第四半导体芯片的第二堆叠。

公开(公告)号：US07023097B2

公开(公告)日：2006-04-04

申请号：US10927952

申请日：2004-08-27

申请人： Jochen Thomas ,  Juergen Grafe ,  Ingo Wennemuth ,  Minka Gospodinova-Daltcheva ,  Maksim Kuzmenka

发明人： Jochen Thomas ,  Juergen Grafe ,  Ingo Wennemuth ,  Minka Gospodinova-Daltcheva ,  Maksim Kuzmenka

IPC分类号： H01L23/48

CPC分类号： H01L24/97 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/06136 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： The invention relates to an FBGA arrangement, comprising a substrate on which at least one chip is chip-bonded face-down, which has a central row of bonding pads connected to contact islands (landing pads) on the substrate by a bonding channel in the substrate via wire bridges, which substrate, for its part, is provided with soldering balls—arranged in an array—for contact connection to a printed circuit board, and the contact islands and the soldering balls being connected to one another via a rewiring of the substrate. The preferred embodiment of the invention is intended to provide an FBGA arrangement which supports the center pad row technology and at the same time has low electrical parasitics. This is achieved by virtue of the fact that at least two substrates (1, 2) are provided, the substrates (1, 2) are provided substratewise in each case with bonding channels (3, 4) having different dimensions, in a manner forming a multistage bonding channel, the bonding channels (3) in the ball-side substrate (2) having larger dimensions than those in the chip-side substrate (1).

摘要翻译： 本发明涉及一种FBGA布置，其包括基板，其上至少一个芯片正面朝下地被芯片接合，该基板具有通过所述基板中的接合通道连接到所述基板上的接触岛（着陆焊盘）的中心排的接合焊盘 衬底通过导线桥接器，该衬底为其部分设置有排列成阵列的焊球，用于与印刷电路板的接触连接，并且接触岛和焊球通过重新布线 基质。 本发明的优选实施例旨在提供一种支持中心焊盘行技术并同时具有低电寄生效应的FBGA布置。 这是通过提供至少两个基板（1,2）的事实来实现的，基板（1,2）以每种形式设置成具有不同尺寸的接合通道（3,4），以形成 多级接合通道，所述球侧基板（2）中的接合通道（3）的尺寸大于所述芯片侧基板（1）的尺寸。

公开(公告)号：US20060043539A1

公开(公告)日：2006-03-02

申请号：US10519444

申请日：2003-06-30

申请人： Jochen Thomas ,  Ingo Wennemuth

发明人： Jochen Thomas ,  Ingo Wennemuth

IPC分类号： H01L23/552

CPC分类号： H01L24/32 ,  B82Y10/00 ,  H01L23/3128 ,  H01L23/49572 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/48 ,  H01L24/50 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/05599 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01052 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/01026 ,  H01L2924/00012

摘要： The invention relates to an electronic component having a multilayered rewiring plate, which carries a circuit chip, in particular a magnetic memory chip, and connects contact areas of the chip to external contacts of the electronic component via rewiring lines. The rewiring plate has at least one patterned, magnetic shielding layer made of an amorphous metal or an amorphous metal alloy. Furthermore, the invention encompasses a method for producing this electronic component.

摘要翻译： 本发明涉及具有多层重新布线板的电子部件，其具有电路芯片，特别是磁性存储器芯片，并且通过再布线将芯片的接触区域连接到电子部件的外部触点。 再配线板具有至少一个由无定形金属或无定形金属合金制成的图案化磁屏蔽层。 此外，本发明包括用于制造该电子部件的方法。

公开(公告)号：US07345363B2

公开(公告)日：2008-03-18

申请号：US11362507

申请日：2006-02-27

申请人： Minka Gospodinova-Daltcheva ,  Harry Huebert ,  Rajesh Subraya ,  Jochen Thomas ,  Ingo Wennemuth

发明人： Minka Gospodinova-Daltcheva ,  Harry Huebert ,  Rajesh Subraya ,  Jochen Thomas ,  Ingo Wennemuth

IPC分类号： H01L23/48

CPC分类号： H01L25/0657 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/552 ,  H01L23/66 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2223/6627 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/49 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06575 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0101 ,  H01L2924/01013 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01052 ,  H01L2924/01068 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/1903 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

摘要： A semiconductor device includes a plastic package, at least one semiconductor chip and a rewiring level. The rewiring level includes an insulating layer and a rewiring layer. The rewiring layer includes either signal conductor paths and ground or supply conductor paths arranged parallel to one another and alternately, or only signal conductor paths arranged parallel to one another. In the latter case, an electrically conducting layer of metal which can be connected to ground or supply potential is additionally provided as a termination of the rewiring level or in the form of a covering layer.

摘要翻译： 半导体器件包括塑料封装，至少一个半导体芯片和重新布线层。 重新布线层包括绝缘层和重新布线层。 重新布线层包括彼此平行布置的信号导体路径和接地或供电导体路径，并且交替地或者仅包括彼此平行布置的信号导体路径。 在后一种情况下，另外提供可连接到接地或供电电位的导电金属层作为重新布线层的终端或覆盖层的形式。

公开(公告)号：US20070210433A1

公开(公告)日：2007-09-13

申请号：US11371204

申请日：2006-03-08

申请人： Rajesh Subraya ,  Helmut Fischer ,  Ingo Wennemuth ,  Minka Gospodinova ,  Jochen Thomas

发明人： Rajesh Subraya ,  Helmut Fischer ,  Ingo Wennemuth ,  Minka Gospodinova ,  Jochen Thomas

IPC分类号： H01L23/02 ,  H01L21/00

CPC分类号： H01L25/0657 ,  H01L23/13 ,  H01L23/3128 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06551 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/06596 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00014 ,  H01L2924/00

摘要： The invention provides an integrated device comprising a plurality of non-individually-encapsulated chip arrangements, each of which having a plurality of contact elements for contacting a contact pad, wherein the plurality of chip arrangements are stacked on each other such that the respective contact elements provide electrical connections to the respective chip arrangement, and a common integral mold arranged to encapsulate the plurality of stacked chip arrangements.

摘要翻译： 本发明提供了一种集成器件，其包括多个非单独封装的芯片布置，每个芯片布置具有用于接触接触焊盘的多个接触元件，其中所述多个芯片布置彼此堆叠，使得各个接触元件 提供到相应芯片布置的电连接，以及布置成封装多个堆叠芯片布置的公共整体模具。

公开(公告)号：US20050156308A1

公开(公告)日：2005-07-21

申请号：US11038574

申请日：2005-01-21

申请人： Anton Legen ,  Jochen Thomas ,  Ingo Wennemuth

发明人： Anton Legen ,  Jochen Thomas ,  Ingo Wennemuth

IPC分类号： H01L21/44 ,  H01L21/60 ,  H01L23/48 ,  H01L23/485 ,  H01L23/495 ,  H01L23/50 ,  H01L25/065 ,  H01R12/50

CPC分类号： H01L24/10 ,  H01L23/495 ,  H01L24/13 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00

摘要： Connecting elements on semiconductor chips for semiconductor components and methods for producing connecting elements provide electrical connections between contact areas of a semiconductor chip and contact pads of a superordinate circuit board. The connecting elements have a bent metal strip with two metal limbs with flattened limb ends. One of the two limb ends is electrically connected to the contact areas, while the second limb end is elastically supported on the top side of the semiconductor chip.

摘要翻译： 用于半导体部件的半导体芯片上的连接元件和用于制造连接元件的方法提供半导体芯片的接触区域和上级电路板的接触焊盘之间的电连接。 连接元件具有弯曲的金属条带，具有两个具有扁平端部的金属四肢。 两个肢端中的一个电连接到接触区域，而第二肢端部弹性地支撑在半导体芯片的顶侧上。

公开(公告)号：US07294910B2

公开(公告)日：2007-11-13

申请号：US10519444

申请日：2003-06-30

申请人： Jochen Thomas ,  Ingo Wennemuth

发明人： Jochen Thomas ,  Ingo Wennemuth

IPC分类号： H01L23/552

CPC分类号： H01L24/32 ,  B82Y10/00 ,  H01L23/3128 ,  H01L23/49572 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/48 ,  H01L24/50 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/05599 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01052 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/01026 ,  H01L2924/00012

摘要： The invention relates to an electronic component having a multilayered rewiring plate, which carries a circuit chip, in particular a magnetic memory chip, and connects contact areas of the chip to external contacts of the electronic component via rewiring lines. The rewiring plate has at least one patterned, magnetic shielding layer made of an amorphous metal or an amorphous metal alloy. Furthermore, the invention encompasses a method for producing this electronic component.

摘要翻译： 本发明涉及具有多层重新布线板的电子部件，其具有电路芯片，特别是磁性存储器芯片，并且通过再布线将芯片的接触区域连接到电子部件的外部触点。 再配线板具有至少一个由无定形金属或无定形金属合金制成的图案化磁屏蔽层。 此外，本发明包括用于制造该电子部件的方法。

公开(公告)号：US20050098870A1

公开(公告)日：2005-05-12

申请号：US10927952

申请日：2004-08-27

申请人： Jochen Thomas ,  Juergen Grafe ,  Ingo Wennemuth ,  Minka Gospodinova-Daltcheva ,  Maksim Kuzmenka

发明人： Jochen Thomas ,  Juergen Grafe ,  Ingo Wennemuth ,  Minka Gospodinova-Daltcheva ,  Maksim Kuzmenka

IPC分类号： H01L23/31 ,  H01L23/498 ,  H01L23/02

CPC分类号： H01L24/97 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/06136 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： The invention relates to an FBGA arrangement, comprising a substrate on which at least one chip is chip-bonded face-down, which has a central row of bonding pads connected to contact islands (landing pads) on the substrate by a bonding channel in the substrate via wire bridges, which substrate, for its part, is provided with soldering balls—arranged in an array—for contact connection to a printed circuit board, and the contact islands and the soldering balls being connected to one another via a rewiring of the substrate. The preferred embodiment of the invention is intended to provide an FBGA arrangement which supports the center pad row technology and at the same time has low electrical parasitics. This is achieved by virtue of the fact that at least two substrates (1, 2) are provided, the substrates (1, 2) are provided substratewise in each case with bonding channels (3, 4) having different dimensions, in a manner forming a multistage bonding channel, the bonding channels (3) in the ball-side substrate (2) having larger dimensions than those in the chip-side substrate (1).

摘要翻译： 本发明涉及一种FBGA布置，其包括基板，其上至少一个芯片正面朝下地被芯片接合，该基板具有通过所述基板中的接合通道连接到所述基板上的接触岛（着陆焊盘）的中心排的接合焊盘 衬底通过导线桥接器，该衬底为其部分设置有排列成阵列的焊球，用于与印刷电路板的接触连接，并且接触岛和焊球通过重新布线 基质。 本发明的优选实施例旨在提供一种支持中心焊盘行技术并同时具有低电寄生效应的FBGA布置。 这是通过提供至少两个基板（1,2）的事实来实现的，基板（1,2）以每种形式设置成具有不同尺寸的接合通道（3,4），以形成 多级接合通道，所述球侧基板（2）中的接合通道（3）的尺寸大于所述芯片侧基板（1）的尺寸。