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    Multiplatform microservice connection techniques
    1.
    发明授权
    Multiplatform microservice connection techniques 有权

    公开(公告)号：US11934896B2

    公开(公告)日：2024-03-19

    申请号：US17966348

    申请日：2022-10-14

    Applicant: NCR Voyix Corporation

    Inventor： Alexander Arrabis Bronola

    IPC: G06F9/54 ,  G06F9/22 ,  G06F9/445 ,  G06Q20/10 ,  G06Q20/18 ,  G06Q20/20

    CPC classification number: G06F9/544 ,  G06F9/22 ,  G06F9/44526 ,  G06F9/546 ,  G06Q20/1085 ,  G06Q20/18 ,  G06Q20/20

    Abstract: Inter-microservice communications are managed through in-memory connection routing. A sending microservice writes a message over a port associated with the connection. The message is routed directly to one or more receiving microservices associated with the connection over their ports associated with the connection. The message may be converted to a different format or multiple different formats through plugins processed when the message is received over the sending microservice's port and before the converting messages are routed over the receiving microservices' ports. The inter-microservice communications are hardware and platform independent or agnostic, such that the microservices associated with the connection can be processed on different hardware and different platforms from one another.

    Availability level-based service management
    4.
    发明授权
    Availability level-based service management 有权

    公开(公告)号：US11714638B2

    公开(公告)日：2023-08-01

    申请号：US16574508

    申请日：2019-09-18

    Applicant: International Business Machines Corporation

    Inventor： Xiao Bin Chen ,  Tianxiang Lu ,  Xin Peng Liu ,  Xiao Jing Fu ,  Jian Huang

    IPC: G06F9/22 ,  G06F8/60 ,  G06F9/455

    CPC classification number: G06F9/22 ,  G06F8/60 ,  G06F9/455

    Abstract: Embodiments of the present disclosure relate to availability level-based service management. In an embodiment, a computer-implemented method is disclosed. According to the method, it is detected initiation of a request from a first microservice to a second microservice. The first and second microservices are comprised in a plurality of microservices of an application. The request comprises an expected availability level for the application. In response to a current availability level of the application being higher than or equal to the expected availability level and in response to determining that the execution of the second microservice is unavailable, the request is caused to be routed to a simulated microservice of the second microservice. The simulated microservice is configured to return to the first microservice a dummy response to the request. In other embodiments, a system and a computer program product are disclosed.

    Microcontroller Or Microprocessor With Dual Mode Interrupt
    10.
    发明申请
    Microcontroller Or Microprocessor With Dual Mode Interrupt 审中-公开
    具有双模式中断的微控制器或微处理器

    公开(公告)号：US20160259741A1

    公开(公告)日：2016-09-08

    申请号：US15060553

    申请日：2016-03-03

    Applicant: Microchip Technology Incorporated

    Inventor： Keith Curtis ,  Ashish Senapati ,  Anthony Garcia ,  Vijay Sarvepalli ,  Prashanth Pulipaka ,  Kevin Kilzer ,  David Forst ,  Rob Kennedy ,  Primo Castro ,  Aaron Barton

    IPC: G06F13/26 ,  G06F9/30 ,  G06F9/22

    CPC classification number: G06F13/26 ,  G06F9/22 ,  G06F9/30036 ,  G06F9/3013 ,  G06F13/24

    Abstract: A microcontroller has a CPU with at least one interrupt input coupled with an interrupt controller, a plurality of peripherals, and a mode register comprising at least one bit controlling an operating mode of the microcontroller. The microcontroller is configured to operate in a first operating mode wherein upon assertion of an interrupt by a peripheral of the microcontroller, the interrupt controller forwards an interrupt signal to the CPU and the peripheral sets an associated interrupt flag, wherein the interrupt causes the CPU to branch to a predefined interrupt address associated with the interrupt input. In a second operating mode, upon assertion of an interrupt by a peripheral of the microcontroller, the interrupt controller forwards an interrupt signal to the CPU and the CPU receives additional interrupt information from the peripheral that generated the interrupt, wherein the additional interrupt information is used to generate a vector address.

    Abstract translation: 微控制器具有CPU，其具有与中断控制器，多个外设耦合的至少一个中断输入，以及包括控制微控制器的操作模式的至少一个位的模式寄存器。 微控制器被配置为在第一操作模式下操作，其中当由微控制器的外设断言中断时，中断控制器将中断信号转发到CPU，并且外设设置相关联的中断标志，其中中断使CPU 分支到与中断输入相关联的预定义中断地址。 在第二操作模式中，当由微控制器的外设断言中断时，中断控制器将中断信号转发到CPU，并且CPU从产生中断的外设接收附加的中断信息，其中使用附加的中断信息 以生成向量地址。

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