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    Semiconductor device having a pair of fins and method of manufacturing the same
    93.
    发明申请
    Semiconductor device having a pair of fins and method of manufacturing the same 失效
    具有一对翅片的半导体器件及其制造方法

    公开(公告)号：US20080111199A1

    公开(公告)日：2008-05-15

    申请号：US11976004

    申请日：2007-10-19

    Applicant: Suk-pil KIM ,  Yoon-dong Park ,  Jong-Jin Lee ,  Won-joo Kim ,  June-mo Koo ,  Seung-hwan Song

    Inventor： Suk-pil KIM ,  Yoon-dong Park ,  Jong-Jin Lee ,  Won-joo Kim ,  June-mo Koo ,  Seung-hwan Song

    IPC: H01L29/76 ,  H01L21/336

    CPC classification number: H01L21/28273 ,  H01L21/28282 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/7881 ,  H01L29/792

    Abstract: Example embodiments relate to a semiconductor device and a method of manufacturing the same. A semiconductor device according to example embodiments may have reduced disturbances during reading operations and a reduced short channel effect. The semiconductor device may include a semiconductor substrate having a body and a pair of fins protruding from the body. Inner spacer insulating layers may be formed on an upper portion of an inner sidewall of the pair of fins so as to reduce the entrance to the region between the pair of fins. A gate electrode may cover a portion of the external sidewalls of the pair of fins and may extend across the inner spacer insulating layers so as to define a void between the pair of fins. Gate insulating layers may be interposed between the gate electrode and the pair of fins.

    Abstract translation: 示例性实施例涉及半导体器件及其制造方法。 根据示例实施例的半导体器件可以在读取操作期间具有减小的干扰，并且减少短信道效应。 半导体器件可以包括具有主体和从主体突出的一对鳍片的半导体衬底。 可以在一对翅片的内侧壁的上部形成内隔离层绝缘层，以减少对一对翅片之间的区域的入口。 栅极电极可以覆盖一对鳍片的外部侧壁的一部分，并且可以跨越内部间隔物绝缘层延伸，以便在一对鳍片之间限定空隙。 栅绝缘层可以插入在栅电极和一对鳍之间。

    Non-volatile memory device and method of manufacturing the non-volatile memory device
    94.
    发明申请
    Non-volatile memory device and method of manufacturing the non-volatile memory device 审中-公开
    非易失性存储器件和制造非易失性存储器件的方法

    公开(公告)号：US20080001209A1

    公开(公告)日：2008-01-03

    申请号：US11783548

    申请日：2007-04-10

    Applicant: Eun-Suk Cho ,  Kyu-Charn Park ,  Jong-Jin Lee ,  Jeong-Dong Choe

    Inventor： Eun-Suk Cho ,  Kyu-Charn Park ,  Jong-Jin Lee ,  Jeong-Dong Choe

    IPC: H01L29/788 ,  H01L21/336

    CPC classification number: H01L29/7883 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/42336

    Abstract: A non-volatile memory device may include a substrate having a field region and an active region including a rounded upper edge portion and a flat upper central portion, an effective tunnel oxide layer on the flat upper central portion of the active region, a split floating gate electrode on the effective tunnel oxide layer, the floating gate electrode having a width greater than a width of the effective tunnel oxide layer, a dielectric layer pattern on the floating gate electrode, the dielectric layer pattern including metal oxide, and a control gate electrode on the dielectric layer pattern.

    Abstract translation: 非易失性存储器件可以包括具有场区域和包括圆形上边缘部分和平坦上中心部分的有源区域的基板，在有源区域的平坦上中心部分上的有效隧道氧化物层，分裂浮动 栅极电极在有效隧道氧化物层上，浮栅电极的宽度大于有效隧道氧化物层的宽度，浮栅电极上的电介质层图案，包括金属氧化物的电介质层图案和控制栅电极 在电介质层图案上。

    Image Sensor Applying Power Voltage to Backside of Semiconductor Substrate and Method of Manufacturing Image Sensor
    95.
    发明申请
    Image Sensor Applying Power Voltage to Backside of Semiconductor Substrate and Method of Manufacturing Image Sensor 审中-公开
    图像传感器将电源电压施加到半导体基板的背面和制造图像传感器的方法

    公开(公告)号：US20070257282A1

    公开(公告)日：2007-11-08

    申请号：US11672866

    申请日：2007-02-08

    Applicant: Yo-han Sun ,  Jong-jin Lee ,  Bum-suk Kim ,  Yun-ho Jang ,  Sae-young Kim ,  Keun-chan Yuk ,  Getman Alexander

    Inventor： Yo-han Sun ,  Jong-jin Lee ,  Bum-suk Kim ,  Yun-ho Jang ,  Sae-young Kim ,  Keun-chan Yuk ,  Getman Alexander

    IPC: H01L27/148 ,  H01L21/339

    CPC classification number: H01L27/14601 ,  H01L27/14687

    Abstract: An image sensor applying a power voltage to a backside of a semiconductor substrate includes a first type semiconductor substrate, a first type semiconductor layer formed on the first type semiconductor substrate, a second type semiconductor layer formed on the first type semiconductor layer, and a power voltage receiver formed on a backside of the first type semiconductor substrate opposite the first type semiconductor layer with respect to the first type semiconductor substrate, wherein the power voltage receiver receives a power voltage from outside and applies the power voltage to the first type semiconductor substrate.

    Abstract translation: 将电源电压施加到半导体衬底的背面的图像传感器包括第一类型半导体衬底，形成在第一类型半导体衬底上的第一类型半导体层，形成在第一类型半导体层上的第二类型半导体层，以及功率 所述电压接收器相对于所述第一类型半导体衬底形成在与所述第一类型半导体层相对的所述第一类型半导体衬底的背面上，其中所述电力电压接收器从外部接收电力电压并将所述电力电压施加到所述第一类型半导体衬底。

    Package substrate manufactured using electrolytic leadless plating process, and method for manufacturing the same
    96.
    发明授权
    Package substrate manufactured using electrolytic leadless plating process, and method for manufacturing the same 失效
    使用电解无铅电镀工艺制造的封装衬底及其制造方法

    公开(公告)号：US07208349B2

    公开(公告)日：2007-04-24

    申请号：US11003737

    申请日：2004-12-06

    Applicant: Jong-Jin Lee ,  Young-Hwan Shin

    Inventor： Jong-Jin Lee ,  Young-Hwan Shin

    IPC: H01L21/44

    CPC classification number: H01L21/4846 ,  H01L21/4857 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H05K3/108 ,  H05K3/243 ,  H05K3/426 ,  H05K2203/1476 ,  Y10T29/49155 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

    Abstract: A method of manufacturing a package substrate includes forming a first copper plated layer on a base substrate having through holes and inner surfaces of the through hole, coating a first resist over the first copper plated layer, partially removing the first resist, forming a second copper plated layer on the first copper plated layer, stripping the first resist, coating a second resist over the resultant structure, and removing the second resist from regions where wire bonding pads and solder ball pads are to be formed, removing exposed portions of the first copper plated layer, forming the wire bonding pads and the solder ball pads, removing the second resist, removing exposed portions of the first copper plated layer, and coating a solder resist over all surfaces of the resultant structure, and removing portions of the solder resist respectively covering the wire bonding pads and the solder ball pads.

    Abstract translation: 一种封装基板的制造方法，其特征在于，在具有贯通孔和贯通孔的内表面的基底基板上形成第一镀铜层，在第一镀铜层上涂布第一抗蚀剂，将第一抗蚀剂部分除去，形成第二铜 镀覆在第一镀铜层上，剥离第一抗蚀剂，在所得结构上涂覆第二抗蚀剂，以及从要形成引线接合焊盘和焊球焊盘的区域去除第二抗蚀剂，去除第一铜的暴露部分 形成引线接合焊盘和焊球焊盘，去除第二抗蚀剂，去除第一镀铜层的暴露部分，以及在所得结构的所有表面上涂覆阻焊剂，分别除去焊料阻挡部分 覆盖引线接合焊盘和焊球垫。

    Radio frequency modulator having C/L delay compensation function, and set-top-box using the same
    97.
    发明授权
    Radio frequency modulator having C/L delay compensation function, and set-top-box using the same 失效
    具有C / L延迟补偿功能的射频调制器，以及使用其的机顶盒

    公开(公告)号：US07079194B2

    公开(公告)日：2006-07-18

    申请号：US10367828

    申请日：2003-02-19

    Applicant: Jong Jin Lee ,  Sang Suk Kim ,  Chae Dong Go ,  Youn Joong Lee ,  Kyoung Soo Kwon

    Inventor： Jong Jin Lee ,  Sang Suk Kim ,  Chae Dong Go ,  Youn Joong Lee ,  Kyoung Soo Kwon

    IPC: H04N5/40

    CPC classification number: H04N5/40 ,  H04N9/77 ,  H04N11/14

    Abstract: An RF modulator includes a C/L delay compensation function of compensating for a delay of a luminance signal with respect to a chrominance signal occurring during demodulating a video signal in a TV set. The RF modulator includes a C/L delay compensation unit delaying a luminance signal by 170 nsec and combining the delayed luminance signal with a chrominance signal to output a composite image signal having a C/l delay of −170 nsec and a frequency modulation unit modulating the video signal received from the C/L delay compensation unit into a high frequency signal of a predetermined broadcasting channel in a single module or package. The RF modulator outputs a video signal having the luminance signal delayed by 170 nsec with respect to the chrominance signal and complies with a C/L delay standard without adding any additional C/L delay compensation unit to the RF modulator.

    Abstract translation: RF调制器包括C / L延迟补偿功能，用于补偿相对于在电视机中解调视频信号期间出现的色度信号的亮度信号的延迟。 RF调制器包括将亮度信号延迟170nsec的C / L延迟补偿单元，并将延迟的亮度信号与色度信号组合以输出具有-170nsec的C / l延迟的合成图像信号，以及调制单元 将从C / L延迟补偿单元接收的视频信号转换为单个模块或封装中的预定广播信道的高频信号。 RF调制器输出相对于色度信号延迟了170nsec的亮度信号的视频信号并且符合C / L延迟标准，而不向RF调制器添加任何额外的C / L延迟补偿单元。

    Method for manufacturing a capacitor for a semiconductor device
    99.
    发明授权
    Method for manufacturing a capacitor for a semiconductor device 失效
    半导体装置用电容器的制造方法

    公开(公告)号：US5700709A

    公开(公告)日：1997-12-23

    申请号：US547901

    申请日：1995-10-25

    Applicant: Won-mo Park ,  Jong-jin Lee

    Inventor： Won-mo Park ,  Jong-jin Lee

    IPC: H01L27/04 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

    CPC classification number: H01L27/10852 ,  H01L27/10817 ,  Y10S148/014

    Abstract: A method for manufacturing a capacitor for a semiconductor device, which includes the steps of forming a first conductive layer on a semiconductor substrate, forming a first pattern by patterning the first conductive layer, sequentially forming a second conductive layer and a first material layer on the entire surface of the resultant structure, forming a spacer on the sidewall of the second conductive layer by anisotropic-etching the first material layer, forming a second pattern by partially etching the second conductive layer and the first pattern, using the spacer as an etching mask, forming a third conductive layer on the entire surface of the resultant structure, forming a cylindrical storage electrode by anisotropic-etching the third conductive layer, and removing the spacer.

    Abstract translation: 一种半导体器件用电容器的制造方法，其特征在于，包括以下步骤：在半导体基板上形成第一导电层，通过图案化第一导电层形成第一图案，在第二导电层上依次形成第二导电层和第一材料层 通过各向异性蚀刻第一材料层在第二导电层的侧壁上形成间隔物，通过使用间隔物作为蚀刻掩模部分蚀刻第二导电层和第一图案来形成第二图案 在所得结构的整个表面上形成第三导电层，通过各向异性蚀刻第三导电层形成圆柱形的存储电极，并且去除间隔物。

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