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    Virtual Ground Non-volatile Memory Array
    91.
    发明申请
    Virtual Ground Non-volatile Memory Array 审中-公开
    虚拟地面非易失性存储器阵列

    公开(公告)号：US20160133639A1

    公开(公告)日：2016-05-12

    申请号：US14935201

    申请日：2015-11-06

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran ,  Hung Quoc Nguyen ,  Nhan Do

    IPC: H01L27/115 ,  G11C16/14 ,  G11C16/26 ,  G11C16/04

    CPC classification number: H01L27/11526 ,  G11C16/0408 ,  G11C16/14 ,  G11C16/26 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/7881

    Abstract: A memory device with memory cell pairs each having a single continuous channel region, first and second floating gates over first and second portions of the channel region, an erase gate over a third portion of the channel region between the first and second channel region portions, and first and second control gates over the first and second floating gates. For each of the pairs of memory cells, the first region is electrically connected to the second region of an adjacent pair of memory cells in the same active region, and the second region is electrically connected to the first region of an adjacent pair of the memory cells in the same active region.

    Abstract translation: 一种存储器件，具有每个具有单个连续沟道区的存储单元对，在沟道区的第一和第二部分上的第一和第二浮置栅极，位于第一和第二沟道区域之间的沟道区的第三部分上的擦除栅极， 以及第一和第二浮动栅极上的第一和第二控制栅极。 对于每对存储器单元，第一区域电连接到相同有源区域中相邻的一对存储器单元的第二区域，并且第二区域电连接到相邻存储器对的第一区域 细胞在相同的活性区域。

    Non-volatile Split Gate Memory Device And A Method Of Operating Same
    92.
    发明申请
    Non-volatile Split Gate Memory Device And A Method Of Operating Same 有权

    公开(公告)号：US20160099067A1

    公开(公告)日：2016-04-07

    申请号：US14506433

    申请日：2014-10-03

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran ,  Hung Quoc Nguyen ,  Nhan Do

    IPC: G11C16/24 ,  G11C16/26 ,  G11C16/04 ,  G11C16/14

    CPC classification number: G11C16/24 ,  G11C16/0408 ,  G11C16/0425 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26

    Abstract: A non-volatile memory device that a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is in the semiconductor substrate arranged in a plurality of rows and columns. Each memory cell comprises a first region on a surface of the semiconductor substrate of a second conductivity type, and a second region on the surface of the semiconductor substrate of the second conductivity type. A channel region is between the first region and the second region. A word line overlies a first portion of the channel region and is insulated therefrom, and adjacent to the first region and having little or no overlap with the first region. A floating gate overlies a second portion of the channel region, is adjacent to the first portion, and is insulated therefrom and is adjacent to the second region. A coupling gate overlies the floating gate. A bit line is connected to the first region. A negative charge pump circuit generates a first negative voltage. A control circuit receives a command signal and generates a plurality of control signals, in response thereto and applies the first negative voltage to the word line of the unselected memory cells. During the operations of program, read or erase, a negative voltage can be applied to the word lines of the unselected memory cells.

    Non-volatile memory program algorithm device and method
    93.
    发明授权
    Non-volatile memory program algorithm device and method 有权

    公开(公告)号：US09293217B2

    公开(公告)日：2016-03-22

    申请号：US14214097

    申请日：2014-03-14

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Xian Liu ,  James Cheng ,  Dmitry Bavinov ,  Alexander Kotov ,  Jong-Won Yoo

    IPC: G11C16/04 ,  G11C16/34 ,  G11C16/12 ,  G11C11/56 ,  G11C16/10

    Abstract: A non-volatile memory device and method for programming cells using repeated pulses of program voltages, with interleaved read operations to determine the level of read current, until the desired programming state is achieved. Each successive program pulse has one or more program voltages increased by a step value relative to the previous pulse. For a single level cell type, each cell is individually removed from the programming pulses after reaching a first read current threshold, and the step value is increased for one or more kicker pulses thereafter. For a multi-level cell type, the step value drops after one of the cells reaches a first read current threshold, some cells are individually removed from the programming pulses after reaching a second read current threshold while others are individually removed from the programming pulses after reaching a third read current threshold.

    Split gate non-volatile flash memory cell having metal-enhanced gates and method of making same
    94.
    发明授权
    Split gate non-volatile flash memory cell having metal-enhanced gates and method of making same 有权
    具有金属增强栅的分闸非易失性闪存单元及其制造方法

    公开(公告)号：US09276006B1

    公开(公告)日：2016-03-01

    申请号：US14589656

    申请日：2015-01-05

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Chun-Ming Chen ,  Man-Tang Wu ,  Jeng-Wei Yang ,  Chien-Sheng Su

    IPC: H01L27/115 ,  H01L21/28 ,  H01L21/02 ,  H01L29/45 ,  H01L29/51 ,  H01L29/49 ,  H01L29/423 ,  H01L29/788 ,  H01L29/66

    CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/4916 ,  H01L29/66825 ,  H01L29/7885

    Abstract: A non-volatile memory cell including a substrate having first and second regions with a channel region therebetween. A floating gate is disposed over and insulated from a first portion of the channel region which is adjacent the first region. A select gate is disposed over and insulated from a second portion of the channel region which is adjacent to the second region. The select gate includes a block of polysilicon material and a work function metal material layer extending along bottom and side surfaces of the polysilicon material block. The select gate is insulated from the second portion of the channel region by a silicon dioxide layer and a high K insulating material layer. A control gate is disposed over and insulated from the floating gate, and an erase gate is disposed over and insulated from the first region, and disposed laterally adjacent to and insulated from the floating gate.

    Abstract translation: 一种非易失性存储单元，包括具有其间具有沟道区的第一和第二区的衬底。 浮置栅极设置在与第一区域相邻的沟道区域的第一部分之上并与其绝缘。 选择栅极设置在与第二区域相邻的沟道区域的第二部分之上并与其绝缘。 选择栅极包括多晶硅材料块和沿着多晶硅材料块的底部和侧表面延伸的功函数金属材料层。 选择栅极通过二氧化硅层和高K绝缘材料层与沟道区的第二部分绝缘。 控制栅极设置在浮动栅极上并与浮动栅极绝缘，并且擦除栅极设置在第一区域的上方并与第一区域绝缘，并且横向地设置在与浮动栅极相邻并与其隔离的位置。

    Method of operating a split gate flash memory cell with coupling gate
    95.
    发明授权
    Method of operating a split gate flash memory cell with coupling gate 有权
    操作具有耦合栅极的分离栅极闪存单元的方法

    公开(公告)号：US09245638B2

    公开(公告)日：2016-01-26

    申请号：US14216776

    申请日：2014-03-17

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Nhan Do ,  Elizabeth A. Cuevas ,  Yuri Tkachev ,  Mandana Tadayoni ,  Henry A. Om'mani

    IPC: G11C16/04 ,  G11C16/26 ,  H01L27/115 ,  G11C16/14

    CPC classification number: G11C16/26 ,  G11C16/0433 ,  G11C16/14 ,  H01L27/115

    Abstract: A method of operating a memory cell that comprises first and second regions spaced apart in a substrate with a channel region therebetween, a floating gate disposed over the channel region and the fir region, a control gate disposed over the channel region and laterally adjacent to the floating gate with a portion disposed over the floating gate, and a coupling gate disposed over the first region and laterally adjacent to the floating gate. A method of erasing the memory cell includes applying a positive voltage to the control gate and a negative voltage to the coupling gate. A method of reading the memory cell includes applying positive voltages to the control gate, to the coupling gate, and to one of the first and second regions.

    Abstract translation: 一种操作存储单元的方法，所述存储单元包括在衬底中间隔开的沟道区域中的第一和第二区域，设置在所述沟道区域和所述冷杉区域上方的浮置栅极，设置在所述沟道区域上方且横向邻近 浮动栅极，其具有设置在浮置栅极上的部分，以及耦合栅极，设置在第一区域上并且横向邻近浮动栅极。 擦除存储单元的方法包括向控制栅极施加正电压，向耦合栅极施加负电压。 读取存储单元的方法包括向控制栅极，耦合栅极以及第一和第二区域之一施加正电压。

    Method Of Forming Extended Source-Drain MOS Transistors
    97.
    发明申请
    Method Of Forming Extended Source-Drain MOS Transistors 审中-公开
    形成扩展源极漏极MOS晶体管的方法

    公开(公告)号：US20150270372A1

    公开(公告)日：2015-09-24

    申请号：US14733904

    申请日：2015-06-08

    Applicant: Silicon Storage Technology, Inc.

    Inventor： CHIEN-SHENG SU ,  MANDANA TADAYONI ,  YUEH-HSIN CHEN

    IPC: H01L29/66 ,  H01L21/265

    CPC classification number: H01L29/66492 ,  H01L21/265 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/7833

    Abstract: A transistor and method of making same include a substrate, a conductive gate over the substrate and a channel region in the substrate under the conductive gate. First and second insulating spacers are laterally adjacent to first and second sides of the conductive gate. A source region in the substrate is adjacent to but laterally spaced from the first side of the conductive gate and the first spacer, and a drain region in the substrate is adjacent to but laterally spaced apart from the second side of the conductive gate and the second spacer. First and second LD regions are in the substrate and laterally extend between the channel region and the source or drain regions respectively, each with a portion thereof not disposed under the first and second spacers nor under the conductive gate, and each with a dopant concentration less than that of the source or drain regions.

    Abstract translation: 晶体管及其制造方法包括衬底，衬底上的导电栅极和导电栅极下的衬底中的沟道区。 第一和第二绝缘间隔件横向邻近导电栅极的第一和第二侧。 衬底中的源极区域与导电栅极和第一间隔物的第一侧相邻但是横向间隔开，并且衬底中的漏极区域与导电栅极的第二侧相邻但横向间隔开，并且第二 间隔 第一LD区域和第二LD区域分别位于衬底中并分别在沟道区域和源极或漏极区域之间横向延伸，每个区域的一部分没有设置在第一和第二间隔物之下，也不设置在导电栅极之下，并且每个具有掺杂剂浓度 比源区或漏区。

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