公开(公告)号：US20140216504A1

公开(公告)日：2014-08-07

申请号：US13760068

申请日：2013-02-06

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Jun XIA ,  Hui LU ,  Li-Sen QIAN ,  Chee-Wei TAN

IPC: B08B3/04

CPC classification number: H01L21/02071 ,  H01L21/02052

Abstract: A silicon wafer cleaning method is provided. Firstly, a silicon wafer is provided. Then, a polymer cleaning step is performed to clean a surface of the silicon wafer. After the polymer cleaning step, a deionized water/carbon dioxide gas discharging step is performed, so that the charges accumulated on the surface of the silicon wafer can be instantly removed. After the deionized water/carbon dioxide gas discharging step, two or more particle removing steps are performed. In addition, an air-jet step is performed during the time interval between every two sub-steps of a single particle removing step. Consequently, the cleaning efficiency of removing the particles will be enhanced.

Abstract translation: 提供硅晶片清洗方法。 首先，提供硅晶片。 然后，进行聚合物清洗工序，清洗硅晶片的表面。 聚合物清洗工序后，进行去离子水/二氧化碳气体排出工序，能够立即除去积聚在硅晶片表面的电荷。 在去离子水/二氧化碳气体排出步骤之后，进行两个以上的除尘步骤。 此外，在单个颗粒除去步骤的每两个子步骤之间的时间间隔期间进行喷气步骤。 因此，除去微粒的清洗效率提高。

公开(公告)号：US20140211573A1

公开(公告)日：2014-07-31

申请号：US14225435

申请日：2014-03-26

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Shi-Wen CHEN ,  Hsin-Pang LU ,  Chung-Cheng TSAI ,  Ya-Nan MOU

IPC: G11C5/14

CPC classification number: G11C5/147 ,  G11C7/00 ,  G11C7/08 ,  G11C7/10 ,  G11C8/08 ,  G11C11/4074 ,  G11C16/30 ,  G11C29/021

Abstract: A supply voltage generation circuit includes a comparison unit, a voltage level control unit and a voltage regulator circuit. Comparison unit is configured to compare input data and output data of a memory array to each other and thereby generating a comparison result, wherein output data are storage data stored in a plurality of memory units of the memory array processed by a program operation according to the input data, and comparison result indicates the number of different bits existing between the output data and the input data. Voltage level control unit is configured to generate a control signal according to the comparison result. Voltage regulator circuit is configured to provide a supply voltage for the memory array and adjust value of the supply voltage according to the control signal. A memory and an operation method of a supply generation circuit used for a memory array are also provided.

Abstract translation: 电源电压产生电路包括比较单元，电压电平控制单元和电压调节器电路。 比较单元被配置为将存储器阵列的输入数据和输出数据彼此进行比较，从而生成比较结果，其中输出数据是存储在存储器阵列的多个存储器单元中的存储数据，该存储器单元根据根据 输入数据和比较结果表示输出数据和输入数据之间存在的不同位数。 电压电平控制单元被配置为根据比较结果产生控制信号。 电压调节器电路被配置为为存储器阵列提供电源电压，并根据控制信号调整电源电压的值。 还提供了用于存储器阵列的供应生成电路的存储器和操作方法。

公开(公告)号：US08703577B1

公开(公告)日：2014-04-22

申请号：US13717638

申请日：2012-12-17

Applicant: United Microelectronics Corporation

Inventor： Meng-Kai Zhu

IPC: H01L21/31 ,  H01L21/311 ,  H01L21/76

CPC classification number: H01L21/3083 ,  H01L21/3081 ,  H01L21/76224

Abstract: A method for fabricating a deep trench isolation structure, wherein the method comprising steps as follows: A first hard mask layer, a second hard mask layer and a third hard mask layer are firstly formed in sequence on a substrate. The third hard mask layer is then patterned using the second hard mask layer as an etching stop layer. Subsequently, a trench etching process is performed using the patterned third hard mask layer as a mask to form a deep trench in the substrate.

Abstract translation: 一种制造深沟槽隔离结构的方法，其中该方法包括以下步骤：首先在衬底上依次形成第一硬掩模层，第二硬掩模层和第三硬掩模层。 然后使用第二硬掩模层作为蚀刻停止层来图案化第三硬掩模层。 随后，使用图案化的第三硬掩模层作为掩模进行沟槽蚀刻工艺，以在衬底中形成深沟槽。

公开(公告)号：US20140099760A1

公开(公告)日：2014-04-10

申请号：US14103827

申请日：2013-12-11

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chieh-Te CHEN ,  Shih-Fang TZOU ,  Jiunn-Hsiung LIAO ,  Yi-Po LIN

IPC: H01L21/28 ,  H01L21/3213 ,  H01L21/321 ,  H01L21/8232 ,  H01L21/027

CPC classification number: H01L21/28079 ,  H01L21/027 ,  H01L21/3212 ,  H01L21/32139 ,  H01L21/8232 ,  H01L27/0629

Abstract: A method for fabricating a semiconductor device, wherein the method comprises steps as follows: A dummy gate with a poly-silicon gate electrode and a passive device having a poly-silicon element layer are firstly provided. A hard mask layer is then formed on the dummy gate and the passive device. Next, a first etching process is performed to remove a portion of the hard mask layer to expose a portion of the poly-silicon element layer. Subsequently, an inner layer dielectric (ILD) is formed on the dummy gate and the poly-silicon element layer, and the ILD is flattened by using the hard mask layer as a polishing stop layer. Thereafter, a second etching process is performed to remove the poly-silicon gate electrode, and a metal gate electrode is formed on the location where the poly-silicon gate electrode was initially disposed.

Abstract translation: 一种制造半导体器件的方法，其中该方法包括以下步骤：首先提供具有多晶硅栅极的伪栅极和具有多晶硅元件层的无源器件。 然后在伪栅极和无源器件上形成硬掩模层。 接下来，执行第一蚀刻工艺以去除硬掩模层的一部分以暴露多晶硅元件层的一部分。 随后，在虚拟栅极和多晶硅元件层上形成内层电介质（ILD），并且通过使用硬掩模层作为抛光停止层使ILD变平。 此后，进行第二蚀刻处理以去除多晶硅栅电极，并且在最初设置多晶硅栅电极的位置处形成金属栅电极。

公开(公告)号：US20130302982A1

公开(公告)日：2013-11-14

申请号：US13943782

申请日：2013-07-16

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chun-Hsing TUNG ,  Fei-Tzu LIN

IPC: H01L21/285

CPC classification number: H01L21/28506 ,  C23C14/3407 ,  C23C14/50 ,  C23C14/505 ,  C23C16/458 ,  C23C16/4584 ,  H01L21/68764 ,  H01L21/68771 ,  H01L21/68785

Abstract: A deposition method comprises steps as follows. An apparatus for performing a thin-film deposition process is firstly provided, and the apparatus comprises a cabinet, a substrate carrier and a deposition source. The substrate carrier is disposed in the cabinet and comprises a cover element and a supporting element having a through hole. The deposition source is disposed in the cabinet. A substrate is subsequently disposed on the supporting element in order to make a deposition surface of the substrate exposed from the through hole. The cover element is then engaged with the supporting element to secure the substrate therebetween. Next, a deposition vapor is provided from the deposition source to get in touch with the deposition surface.

Abstract translation: 沉积方法包括以下步骤。 首先提供用于执行薄膜沉积工艺的设备，并且该设备包括机柜，基板载体和沉积源。 衬底载体设置在机壳中，并且包括覆盖元件和具有通孔的支撑元件。 沉积源设置在机柜中。 随后将基板设置在支撑元件上，以使基板的沉积表面从通孔露出。 盖元件然后与支撑元件接合以将基板固定在其间。 接下来，从沉积源提供沉积蒸气以与沉积表面接触。

公开(公告)号：US08553911B2

公开(公告)日：2013-10-08

申请号：US13665935

申请日：2012-11-01

Applicant: United Microelectronics Corporation

Inventor： Li-Che Chen

IPC: H04R7/02

CPC classification number: B81B3/0078 ,  B81B2201/0257 ,  B81B2203/0127 ,  H04R7/06 ,  H04R19/005 ,  H04R19/04

Abstract: A diaphragm of an MEMS electroacoustic transducer including a first axis-symmetrical pattern layer is provided. Because the layout of the first axis-symmetrical pattern layer can match the pattern of the sound wave, the vibration uniformity of the diaphragm can be improved.

Abstract translation: 提供了包括第一轴对称图案层的MEMS电声换能器的隔膜。 由于第一轴对称图案层的布局可以匹配声波的图案，所以可以提高隔膜的振动均匀性。

公开(公告)号：US20130260524A1

公开(公告)日：2013-10-03

申请号：US13902866

申请日：2013-05-27

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chien-Hung CHEN ,  Tzu-Ping CHEN ,  Yu-Jen CHANG

IPC: H01L29/66

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/4234 ,  H01L29/66833

Abstract: A method for manufacturing a non-volatile memory is disclosed. A gate structure is formed on a substrate and includes a gate dielectric layer and a gate conductive layer. The gate dielectric layer is partly removed, thereby a symmetrical opening is formed among the gate conductive layer, the substrate and the gate dielectric layer, and a cavity is formed on end sides of the gate dielectric layer. A first oxide layer is formed on a sidewall and bottom of the gate conductive layer, and a second oxide layer is formed on a surface of the substrate. A nitride material layer is formed covering the gate structure, the first and second oxide layer and the substrate and filling the opening. An etching process is performed to partly remove the nitride material layer, thereby forming a nitride layer on a sidewall of the gate conductive layer and extending into the opening.

Abstract translation: 公开了一种用于制造非易失性存储器的方法。 栅极结构形成在衬底上，并且包括栅极介电层和栅极导电层。 部分地去除栅介质层，从而在栅极导电层，基板和栅极电介质层之间形成对称的开口，并且在栅极电介质层的端侧上形成空洞。 在栅极导电层的侧壁和底部上形成第一氧化物层，并且在衬底的表面上形成第二氧化物层。 形成覆盖栅极结构，第一和第二氧化物层和衬底并填充开口的氮化物材料层。 执行蚀刻处理以部分地去除氮化物材料层，从而在栅极导电层的侧壁上形成并延伸到开口中的氮化物层。

公开(公告)号：US20130087810A1

公开(公告)日：2013-04-11

申请号：US13689720

申请日：2012-11-29

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Teng-Chun TSAI ,  Chun-Yuan WU ,  Chin-Fu LIN ,  Chih-Chien LIU ,  Chin-Cheng CHIEN

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7833

Abstract: A fin field-effect transistor structure comprises a substrate, a fin channel, a source/drain region, a high-k metal gate and a plurality of slot contact structures. The fin channel is formed on the substrate. The source/drain region is formed in the fin channel. The high-k metal gate formed on the substrate and the fin channel comprises a high-k dielectric layer and a metal gate layer, wherein the high-k dielectric layer is arranged between the metal gate layer and the fin channel. The slot contact structures are disposed at both sides of the metal gate.

Abstract translation: 鳍状场效应晶体管结构包括衬底，鳍状沟道，源极/漏极区域，高k金属栅极和多个狭槽接触结构。 翅片通道形成在基板上。 源极/漏极区域形成在鳍状沟道中。 形成在基板和鳍状沟道上的高k金属栅包括高k电介质层和金属栅极层，其中高k电介质层布置在金属栅极层和鳍状沟之间。 槽接触结构设置在金属门的两侧。

公开(公告)号：US20250169208A1

公开(公告)日：2025-05-22

申请号：US19032468

申请日：2025-01-21

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Hau-Yuan Huang ,  Chia-Chen Tsai ,  Jia-Bin Yeh ,  Shou-Wei Hsieh

IPC: H10F39/00

Abstract: Provided is a manufacturing method of an NMOS structure that includes a semiconductor substrate, a dielectric structure, a source/drain doped region, a channel region, a gate structure and two isolation P-type wells. The dielectric structure is formed in the semiconductor substrate to define an active region, in which the source/drain doped region and the channel region are formed. The channel region includes two opposite first sides and two opposite second sides. The source/drain doped region is respectively formed between the two second sides and the dielectric structure. The gate structure is formed on the semiconductor substrate. The gate structure covers a part of the dielectric structure beside the first sides. The two isolation P-type wells are formed in a part of the dielectric structure not covered by the gate structure. The isolation P-type wells respectively surround a periphery of the source/drain doped region and end at the respective second side.

公开(公告)号：US12272662B2

公开(公告)日：2025-04-08

申请号：US17739213

申请日：2022-05-09

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chien-Ming Lai ,  Zhi-Rui Sheng ,  Hui-Ling Chen

IPC: H01L23/522 ,  H01L23/00 ,  H10D1/20 ,  H10D1/47 ,  H10D1/68

Abstract: A semiconductor structure includes a first layer, a second layer, a first interconnection layer, and a second interconnection layer. The first layer includes an upper passive component pattern, and the second layer includes a lower passive component pattern, wherein the upper passive component pattern is opposite to the lower passive component pattern. The first interconnection layer includes at least one first interconnect structure electrically connected on the upper passive component pattern. The second interconnection layer includes at least one second interconnect structure electrically connected on the passive component pattern. The first interconnect structure on the upper passive component pattern is hybrid bonded with the second interconnect structure on the lower passive component pattern. Therefore, the upper passive component pattern and the lower passive component pattern are joined by hybrid bonding to form a passive device.