公开(公告)号：US20070280358A1

公开(公告)日：2007-12-06

申请号：US11753307

申请日：2007-05-24

申请人： Sherman Chen ,  Alexander MacInnis

发明人： Sherman Chen ,  Alexander MacInnis

IPC分类号： H04N7/12

CPC分类号： H04N21/23608 ,  H04N7/0112 ,  H04N7/012 ,  H04N21/4307 ,  Y10S348/911

摘要： Systems and methods of coding progressive content with isolated fields for conversion to interlaced display are provided. Some systems and methods may find use in, for example, digital video compression systems and methods. Film material may be encoded as video material with an intended field polarity and an explicit 3:2 pull-down operation for interlaced display (e.g., a 30-frames-per-second display).

摘要翻译： 提供了将逐行内容编码为具有用于转换为隔行显示的孤立字段的系统和方法。 一些系统和方法可以用于例如数字视频压缩系统和方法。 胶片材料可以被编码为具有期望的场极性的视频材料和用于隔行显示的显式3：2下拉操作（例如，每秒30帧的显示）。

公开(公告)号：US20070120874A1

公开(公告)日：2007-05-31

申请号：US11441782

申请日：2006-05-26

申请人： Alexander MacInnis ,  Chengfuh Tang ,  Xiaodong Xie ,  James Patterson ,  Greg Kranawetter

发明人： Alexander MacInnis ,  Chengfuh Tang ,  Xiaodong Xie ,  James Patterson ,  Greg Kranawetter

IPC分类号： G09G5/00

CPC分类号： G09G5/001 ,  G09G5/06 ,  G09G5/12 ,  G09G5/14 ,  G09G5/28 ,  G09G5/346 ,  G09G5/363 ,  G09G5/395 ,  G09G2310/0224 ,  G09G2320/0247 ,  G09G2340/0407 ,  G09G2340/10 ,  G09G2340/125 ,  G09G2360/121 ,  G09G2360/125

摘要： A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The chip includes a display engine that processes graphics images organized as windows. The system includes plurality of line buffers for receiving the graphics contents. The graphics contents are composited into each of the plurality of line buffers by blending the graphics contents with the existing contents of the line buffer until all of the graphics surfaces for the line have been composited.

摘要翻译： 在用于控制电视显示器的机顶盒中使用图形集成电路芯片。 图形芯片同时处理模拟视频输入，数字视频输入，图形输入和音频输入。 该芯片包括一个显示引擎，用于处理组织为Windows的图形图像。 该系统包括用于接收图形内容的多个行缓冲器。 将图形内容通过将图形内容与行缓冲存储器的现有内容进行混合直到所有行的所有图形表面都被合成，来合成到多个行缓冲器的每一行中。

公开(公告)号：US20070089114A1

公开(公告)日：2007-04-19

申请号：US11550767

申请日：2006-10-18

申请人： Alexander MacInnis

发明人： Alexander MacInnis

IPC分类号： G06F9/46

CPC分类号： G06F9/4887 ,  G06F9/4843 ,  G06F9/50 ,  G06F9/5038 ,  G06F13/18

摘要： In one embodiment of the present invention, there is presented computer readable media for servicing at least one task. The machine readable media stores a plurality of instructions, where the plurality of instructions further comprises an operating system. The operating system treats a first request from a task at a priority level associated with a real time application and treats subsequent requests from the task that occur within a predetermined amount of time after the first request at another priority level that is lower than the priority level associated with the task. In another embodiment, an operating system receives real time requirements from at least one task and determines whether it can assure the task of meeting its real time requirements.

摘要翻译： 在本发明的一个实施例中，提供了用于维护至少一个任务的计算机可读介质。 机器可读介质存储多个指令，其中多个指令还包括操作系统。 操作系统处理来自与实时应用相关联的优先级的任务的第一请求，并且处理在第一请求之后的预定时间量内发生的任务的后续请求在低于优先级的另一优先级 与任务相关联。 在另一个实施例中，操作系统从至少一个任务接收实时要求，并确定是否可以确保满足其实时要求的任务。

公开(公告)号：US20070086517A1

公开(公告)日：2007-04-19

申请号：US11516262

申请日：2006-09-06

申请人： Alexander MacInnis

发明人： Alexander MacInnis

IPC分类号： H04B1/66

CPC分类号： H04N19/00587 ,  H04N19/132 ,  H04N19/137 ,  H04N19/14 ,  H04N19/172 ,  H04N19/51 ,  H04N19/587 ,  H04N19/61

摘要： Described herein are a method and system for frame rate adaptation. There may be conditions that require the rate of a video sequence to be dynamically controlled, and a frame interval may be adaptively selected every frame. A frame within the video sequence may contain, for example, a time stamp that is transmitted to a decoder to indicate the change in temporal spacing between frames.

摘要翻译： 这里描述了用于帧速率适配的方法和系统。 可能存在要求动态控制视频序列的速率的条件，并且可以每帧自适应地选择帧间隔。 视频序列内的帧可以包含例如发送到解码器以指示帧之间的时间间隔的变化的时间戳。

公开(公告)号：US20070030276A1

公开(公告)日：2007-02-08

申请号：US11485582

申请日：2006-07-12

申请人： Alexander MacInnis ,  Chengfuh Tang ,  Greg Kranawetter

发明人： Alexander MacInnis ,  Chengfuh Tang ,  Greg Kranawetter

IPC分类号： G06F15/80

CPC分类号： G06T9/007 ,  G09G5/001 ,  G09G5/02 ,  G09G5/024 ,  G09G5/026 ,  G09G5/06 ,  G09G5/12 ,  G09G5/14 ,  G09G5/28 ,  G09G5/346 ,  G09G5/36 ,  G09G5/363 ,  G09G2300/0408 ,  G09G2310/0224 ,  G09G2320/0247 ,  G09G2340/02 ,  G09G2340/0407 ,  G09G2340/0428 ,  G09G2340/06 ,  G09G2340/10 ,  G09G2340/12 ,  G09G2340/125 ,  G09G2360/02 ,  G09G2360/121 ,  G09G2360/125 ,  G09G2360/126 ,  G09G2360/128 ,  H04N5/126 ,  H04N5/14 ,  H04N5/4401 ,  H04N5/44504 ,  H04N5/44508 ,  H04N5/44591 ,  H04N5/45 ,  H04N5/46 ,  H04N9/45 ,  H04N9/641 ,  H04N9/642 ,  H04N9/75 ,  H04N9/78 ,  H04N11/143 ,  H04N11/20 ,  H04N19/112 ,  H04N19/16 ,  H04N19/186 ,  H04N19/20 ,  H04N19/27 ,  H04N19/42 ,  H04N19/423 ,  H04N19/436 ,  H04N19/44 ,  H04N19/59 ,  H04N19/61 ,  H04N19/80 ,  H04N21/42204 ,  H04N21/42653 ,  H04N21/4305 ,  H04N21/4316 ,  H04N21/434 ,  H04N21/4438 ,  H04N21/47

摘要： A display engine of a video and graphics system includes one or more processing elements and receives graphics from a memory. The graphics data define multiple graphics layers, and the processing elements process two or more graphics layers in parallel to generate blended graphics. Alpha values may be used while blending graphics. The processing elements may be integrated on an integrated circuit chip with an input for receiving the graphics data and other video and graphics components. The display engine may also include a graphics controller for receiving two or more graphics layers in parallel, for arranging the graphics layers in an order suitable for parallel processing, and for providing the arranged graphics layers to the processing elements. The blended graphics may be blended with HDTV video or SDTV video, which may be extracted from compressed data streams such as an MPEG Transport stream.

摘要翻译： 视频和图形系统的显示引擎包括一个或多个处理元件并从存储器接收图形。 图形数据定义多个图形层，并且处理元件并行处理两个或多个图形层以产生混合图形。 混合图形时可以使用Alpha值。 处理元件可以集成在具有用于接收图形数据和其他视频和图形部件的输入的集成电路芯片上。 显示引擎还可以包括用于并行接收两个或更多图形层的图形控制器，用于以适于并行处理的顺序排列图形层，以及为处理元件提供布置的图形层。 混合图形可以与HDTV视频或SDTV视频混合，HDTV视频或SDTV视频可以从诸如MPEG传输流的压缩数据流中提取。

公开(公告)号：US20070014368A1

公开(公告)日：2007-01-18

申请号：US11485667

申请日：2006-07-13

申请人： Alexander MacInnis ,  Sheng Zhong

发明人： Alexander MacInnis ,  Sheng Zhong

IPC分类号： H04N11/04 ,  H04B1/66

CPC分类号： H04N19/00703 ,  H04N5/145 ,  H04N5/21 ,  H04N19/521 ,  H04N19/85

摘要： Described herein is a method and system for the reduction of noise in a video sequence. When motion is present in the video sequence, this system and method identifies motion data. With the motion data, a Motion Compensated Temporal Filter (MCTF) can apply motion compensation prior to filtering in the time domain. Temporal filtering can be performed to reduce visible noise and other detrimental artifacts.

摘要翻译： 这里描述了一种用于减少视频序列中的噪声的方法和系统。 当视频序列中存在运动时，该系统和方法识别运动数据。 使用运动数据，运动补偿时间滤波器（MCTF）可以在时域滤波之前应用运动补偿。 可以进行时间滤波以减少可见噪声和其他有害的伪影。

公开(公告)号：US20070013815A1

公开(公告)日：2007-01-18

申请号：US11486323

申请日：2006-07-13

申请人： Alexander MacInnis

发明人： Alexander MacInnis

IPC分类号： H04N17/00 ,  H04N5/00

CPC分类号： H04N17/00 ,  H04N9/646 ,  H04N17/02

摘要： Described herein is a method and system for video sequence evaluation in the presence of cross-chroma interference. When the luma and chroma components in an analog video sequence are separated, the luma component may add interference to the chroma component. This is called cross-chroma interference. In the evaluation of the video sequence, the cross-chroma interference may be interpreted as motion, noise, or other artifacts. By reducing the cross-chroma interference during the evaluation, motion and noise can be identified with greater probability. The proper identification can aid motion estimators used in video coding and motion compensated temporal filtering, and it can aid video filters that do not utilize motion compensation.

摘要翻译： 这里描述了在存在交叉色度干扰的情况下用于视频序列评估的方法和系统。 当模拟视频序列中的亮度和色度分量分离时，亮度分量可能会增加色度分量的干扰。 这被称为交叉色度干扰。 在视频序列的评估中，交叉色度干扰可以被解释为运动，噪声或其他伪像。 通过在评估期间减少交叉色度干扰，可以更大的概率识别运动和噪声。 适当的识别可以帮助用于视频编码和运动补偿时间滤波的运动估计器，并且它可以帮助不利用运动补偿的视频滤波器。

公开(公告)号：US20060280374A1

公开(公告)日：2006-12-14

申请号：US11466328

申请日：2006-08-22

申请人： Vivian Hsiun ,  Alexander MacInnis ,  Xiaodong Xie ,  Sheng Zhong

发明人： Vivian Hsiun ,  Alexander MacInnis ,  Xiaodong Xie ,  Sheng Zhong

IPC分类号： G06K9/36

CPC分类号： H04N19/90 ,  H04N19/12 ,  H04N19/122 ,  H04N19/129 ,  H04N19/157 ,  H04N19/176 ,  H04N19/423 ,  H04N19/44 ,  H04N19/60 ,  H04N19/61 ,  H04N19/70 ,  H04N19/82 ,  H04N19/91

摘要： The present invention provides an apparatus and method for providing a programmable inverse discrete cosine transform, wherein the transform coefficients are loaded into a memory area of a core transform device and a variety of coding standards can thereby be handled by the same programmable core device. The core device is configured to process a certain sized data block, and the incoming source blocks are converted to conform to this size. After transformation, the proper sized result can be extracted from the transform device output. A switchable speed-up mode provides for 4-point transforms, rather than 8-point transforms. Alternatively, the invention also provides for dedicated transform hardware to be switchably used in conjunction with programmable transform hardware, depending upon the type of coding being used, and the speed of inverse transform desired.

摘要翻译： 本发明提供了一种用于提供可编程逆离散余弦变换的装置和方法，其中变换系数被加载到核心变换设备的存储区域中，并且各种编码标准由此可由相同的可编程核心设备处理。 核心设备被配置为处理某个大小的数据块，并且将输入的源块转换为符合该大小。 转换后，可以从变换设备输出中提取适当大小的结果。 可切换的加速模式提供4点变换，而不是8点变换。 或者，本发明还提供了根据所使用的编码类型以及期望的逆变换速度，可编程变换硬件可切换地使用的专用变换硬件。

公开(公告)号：US20060232868A1

公开(公告)日：2006-10-19

申请号：US11426836

申请日：2006-06-27

申请人： David Wu ,  Hoang Nhu ,  Russ Lambert ,  Alexander MacInnis ,  Ronald Crochiere

发明人： David Wu ,  Hoang Nhu ,  Russ Lambert ,  Alexander MacInnis ,  Ronald Crochiere

IPC分类号： G11B25/04

CPC分类号： H04N7/06 ,  H04H20/48 ,  H04N5/602 ,  H04N5/607 ,  H04N21/8106 ,  H04N21/85406 ,  H04R5/04

摘要： A system and method are disclosed for performing digital multi-channel decoding of a BTSC composite audio signal. Each subsequent stage of the digital multi-channel decoding process is performed at the lowest sampling rate that yields acceptable performance for that stage. Analog-to-digital conversion of the composite audio signal is performed first to generate a composite digital audio signal. After analog-to-digital conversion, all signal processing may be performed in the digital domain. The composite digital audio signal is digitally filtered to frequency compensate for variations caused by previous stages of processing, including IF demodulation. Digital channel demodulation and filtering are performed to isolate single channels of the composite digital audio signal such as SAP, L−R, and L+R channels. SAP and L−R channels are DBX decoded resulting in corresponding decoded signals using a unique combination of digital filters that are an efficient translation of a corresponding combination of analog filters. The decoded L−R channel and the L+R channel are re-matrixed to form left and right stereo signals. Any of the SAP signal, left and right stereo signals, and L+R channel signal may be sample rate converted and output at a standard audio output rate.

摘要翻译： 公开了一种用于对BTSC复合音频信号执行数字多声道解码的系统和方法。 数字多通道解码过程的每个后续阶段以最低的采样率执行，该阶段产生可接受的性能。 首先执行复合音频信号的模数转换以产生复合数字音频信号。 在模数转换之后，可以在数字域中执行所有的信号处理。 复合数字音频信号被数字滤波，以对由先前的处理阶段（包括IF解调）引起的变化进行频率补偿。 执行数字信道解调和滤波以隔离诸如SAP，L-R和L + R信道的复合数字音频信号的单个信道。 SAP和L-R通道被DBX解码，从而产生相应的解码信号，其使用数字滤波器的独特组合，其是模拟滤波器的相应组合的有效转换。 解码的L-R信道和L + R信道被重新矩阵化以形成左和右立体声信号。 SAP信号，左立体声信号和右立体声信号以及L + R信道信号中的任何一个可以采样率转换并以标准音频输出速率输出。

公开(公告)号：US20060193383A1

公开(公告)日：2006-08-31

申请号：US11400949

申请日：2006-04-05

申请人： Jose Alvarez ,  Alexander MacInnis ,  Sheng Zhong ,  Xiaodong Xie ,  Vivian Hsium

发明人： Jose Alvarez ,  Alexander MacInnis ,  Sheng Zhong ,  Xiaodong Xie ,  Vivian Hsium

IPC分类号： H04B1/66 ,  H04N11/04 ,  H04N11/02 ,  H04N7/12

CPC分类号： G06F9/3861 ,  G06F9/3877 ,  H04N19/12 ,  H04N19/122 ,  H04N19/129 ,  H04N19/13 ,  H04N19/157 ,  H04N19/176 ,  H04N19/423 ,  H04N19/44 ,  H04N19/60 ,  H04N19/61 ,  H04N19/70 ,  H04N19/82 ,  H04N19/90

摘要： A system and method for decoding a digital video data stream. In one aspect, a plurality of hardware acceleration modules are used together with a core processor. The accelerators operate in a decoding pipeline wherein, in any given stage, each accelerator operates on a particular macroblock of video data. In the subsequent pipeline stage, each accelerator works on the next macroblock in the data stream, which was worked on by another one of the accelerators in the previous stage. The core processor polls all of the accelerators during each stage. When all accelerators finish their tasks for a given stage, the core processor initiates the next stage. In another aspect, two variable-length decoders are employed to simultaneously decode two macroblock rows of a video frame. Each variable-length decoder works to decode an assigned row and the rows are variable-length decoded in parallel. The variable-length decoders operate as part of a pipeline wherein the variable-length decoders alternate, stage-by-stage, decoding macroblocks.