公开(公告)号：US20240213118A1

公开(公告)日：2024-06-27

申请号：US18088545

申请日：2022-12-24

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Heli Chetanbhai VORA ,  Samuel James BADER ,  Ahmad ZUBAIR ,  Thomas HOFF ,  Pratik KOIRALA ,  Michael S. BEUMER ,  Paul NORDEEN ,  Nityan NAIR

IPC: H01L23/48 ,  H01L23/528 ,  H01L23/532 ,  H01L23/66 ,  H01L29/20 ,  H01L29/40 ,  H01L29/778 ,  H01P3/00

CPC classification number: H01L23/481 ,  H01L23/5286 ,  H01L23/53228 ,  H01L23/66 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/7786 ,  H01P3/003 ,  H01L2223/6627

Abstract: Gallium nitride (GaN) devices with through-silicon vias for integrated circuit technology are described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, the layer including gallium and nitrogen above a silicon substrate. A backside structure is below the silicon substrate and opposite the layer including gallium and nitrogen, the backside structure including conductive features and dielectric structures. The integrated circuit structure also includes a plurality of through-silicon via power bars having a staggered arrangement, individual ones of the through-silicon via power bars extending through the layer including gallium and nitrogen and through the silicon substrate to a corresponding one of the conductive features of the backside structure, and individual ones of the through-silicon via power bars having a tapered portion coupled to an essentially vertical portion.

公开(公告)号：US20240128269A1

公开(公告)日：2024-04-18

申请号：US18396360

申请日：2023-12-26

Applicant: Intel Corporation

Inventor： Abhishek A. SHARMA ,  Van H. LE ,  Seung Hoon SUNG ,  Ravi PILLARISETTY ,  Marko RADOSAVLJEVIC

IPC: H01L27/12 ,  G05F1/56 ,  G06F1/26 ,  H01L21/02 ,  H01L21/383 ,  H01L29/24 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/1207 ,  G05F1/56 ,  G06F1/26 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/02192 ,  H01L21/02565 ,  H01L21/383 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696 ,  H01L2029/42388

Abstract: Described herein are apparatuses, systems, and methods associated with a voltage regulator circuit that includes one or more thin-film transistors (TFTs). The TFTs may be formed in the back-end of an integrated circuit. Additionally, the TFTs may include one or more unique features, such as a channel layer treated with a gas or plasma, and/or a gate oxide layer that is thicker than in prior TFTs. The one or more TFTs of the voltage regulator circuit may improve the operation of the voltage regulator circuit and free up front-end substrate area for other devices. Other embodiments may be described and claimed.

公开(公告)号：US20240088153A1

公开(公告)日：2024-03-14

申请号：US18513028

申请日：2023-11-17

Applicant: Intel Corporation

Inventor： Nicole THOMAS ,  Ehren MANNEBACH ,  Cheng-Ying HUANG ,  Marko RADOSAVLJEVIC

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/0922 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/823807 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a selective bottom-up approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxide nanowires. A first gate stack is over and around the one or more active nanowires. A second gate stack is over and around the one or more oxide nanowires.

公开(公告)号：US20210408257A1

公开(公告)日：2021-12-30

申请号：US16911705

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Nicole THOMAS ,  Michael K. HARPER ,  Leonard P. GULER ,  Marko RADOSAVLJEVIC ,  Thoe MICHAELOS

IPC: H01L29/423 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/02

Abstract: Embodiments disclosed herein include semiconductor devices and methods of making such devices. In an embodiment, the semiconductor device comprises a plurality of stacked semiconductor channels comprising first semiconductor channels and second semiconductor channels over the first semiconductor channels. In an embodiment a spacing is between the first semiconductor channels and the second semiconductor channels. The semiconductor device further comprises a gate dielectric surrounding individual ones of the semiconductor channels of the plurality of stacked semiconductor channels. In an embodiment, a first workfunction metal surrounds the first semiconductor channels, and a second workfunction metal surrounds the second semiconductor channels.

公开(公告)号：US20210288049A1

公开(公告)日：2021-09-16

申请号：US17334425

申请日：2021-05-28

Applicant: Intel Corporation

Inventor： Ravi PILLARISETTY ,  Willy RACHMADY ,  Marko RADOSAVLJEVIC ,  Van H. LE ,  Jack T. KAVALIEROS

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238

Abstract: Techniques and mechanisms for operating transistors that are in a stacked configuration. In an embodiment, an integrated circuit (IC) device includes transistors arranged along a line of direction which is orthogonal to a surface of a semiconductor substrate. A first epitaxial structure and a second epitaxial structure are coupled, respectively, to a first channel structure of a first transistor and a second channel structure of a second transistor. The first epitaxial structure and the second epitaxial structure are at different respective levels relative to the surface of the semiconductor substrate. A dielectric material is disposed between the first epitaxial structure and the second epitaxial structure to facilitate electrical insulation of the channels from each other. In another embodiment, the stacked transistors are coupled to provide a complementary metal-oxide-semiconductor (CMOS) inverter circuit.

公开(公告)号：US20200098754A1

公开(公告)日：2020-03-26

申请号：US16606702

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Ravi PILLARISETTY ,  Willy RACHMADY ,  Marko RADOSAVLJEVIC ,  Van H. LE ,  Jack T. KAVALIEROS

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238

Abstract: Techniques and mechanisms for operating transistors that are in a stacked configuration. In an embodiment, an integrated circuit (IC) device includes transistors arranged along a line of direction which is orthogonal to a surface of a semiconductor substrate. A first epitaxial structure and a second epitaxial structure are coupled, respectively, to a first channel structure of a first transistor and a second channel structure of a second transistor. The first epitaxial structure and the second epitaxial structure are at different respective levels relative to the surface of the semiconductor substrate. A dielectric material is disposed between the first epitaxial structure and the second epitaxial structure to facilitate electrical insulation of the channels from each other. In another embodiment, the stacked transistors are coupled to provide a complementary metal-oxide-semiconductor (CMOS) inverter circuit.

公开(公告)号：US20190393332A1

公开(公告)日：2019-12-26

申请号：US16016411

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA ,  Paul FISCHER ,  Walid HAFEZ

IPC: H01L29/778 ,  H01L29/08 ,  H01L29/20 ,  H01L29/205 ,  H01L21/02 ,  H01L29/66

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate, an epitaxial layer on the substrate, a semiconductor interlayer on top of the epitaxial layer, a gate conductor above the semiconductor interlayer, a gate insulator on the bottom and sides of the gate conductor and contacting the top surface of the semiconductor interlayer, a source region extending into the epitaxial layer, and a drain region extending into the epitaxial layer. The semiconductor device also includes a first polarization layer on the semiconductor interlayer between the source region and the gate conductor and a second polarization layer on the semiconductor interlayer between the drain region and the gate conductor.

公开(公告)号：US20190393210A1

公开(公告)日：2019-12-26

申请号：US16016396

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Paul FISCHER ,  Walid HAFEZ

IPC: H01L27/02 ,  H01L29/20 ,  H01L29/06 ,  H01L29/872 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L21/265

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate, an epitaxial layer above the substrate, a Schottky barrier material on the epitaxial layer, a Schottky metal contact extending into the Schottky barrier material, a fin structure that extends in a first direction, a first angled implant in a first side of the fin structure that has an orientation that is orthogonal to the first direction, and a second angled implant in a second side of the fin structure that has an orientation that is orthogonal to the first direction. The second side is opposite to the first side. A first cathode region and a second cathode region are coupled by parts of the first angled implant and the second angled implant that extend in the first direction.

公开(公告)号：US20190393041A1

公开(公告)日：2019-12-26

申请号：US16013860

申请日：2018-06-20

Applicant: Intel Corporation

Inventor： Marko RADOSAVLJEVIC ,  Han Wui THEN ,  Sansaptak DASGUPTA ,  Paul FISCHER ,  Walid HAFEZ

IPC: H01L21/28 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/51 ,  H01L29/49 ,  H01L29/778 ,  H01L29/66

Abstract: A transistor gate is disclosed. The transistor gate includes a first part above a substrate that has a first width and a second part above the first part that is centered with respect to the first part and that has a second width that is greater than the first width. The first part and the second part form a single monolithic T-gate structure.

公开(公告)号：US20190207003A1

公开(公告)日：2019-07-04

申请号：US16326857

申请日：2016-09-29

Applicant: INTEL CORPORATION

Inventor： Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA ,  Han Wui THEN

IPC: H01L29/20 ,  H01L29/08 ,  H01L29/205 ,  H01L29/66

CPC classification number: H01L29/2003 ,  H01L29/0847 ,  H01L29/0895 ,  H01L29/205 ,  H01L29/66522 ,  H01L29/66545

Abstract: Methods and apparatus for semiconductor manufacture are disclosed. An example apparatus includes a Gallium Nitride (GaN) substrate; a p-type GaN region positioned on the GaN substrate; a p-type Indium Nitride (InN) region positioned on the GaN substrate and sharing an interface with the p-type GaN region; and a n-type Indium Gallium Nitride (InGaN) region positioned on the GaN substrate and sharing an interface with the p-type InN region.