公开(公告)号：US12033856B2

公开(公告)日：2024-07-09

申请号：US17489018

申请日：2021-09-29

Applicant: International Business Machines Corporation

Inventor： Yann Mignot ,  Ekmini Anuja De Silva ,  Dario Goldfarb

IPC: H01L21/033 ,  H01L21/311

CPC classification number: H01L21/0332 ,  H01L21/31144

Abstract: A method of forming a multi color resist structure includes providing a substrate including an underlayer material; forming a first organic planarizing layer on the substrate; forming a first anti reflecting layer on the first organic planarizing layer, forming and developing a first patterned resist on the first anti reflecting layer; forming a second organic planarizing layer on the first anti reflecting layer and on the first patterned resist; forming a second anti reflecting layer on the second organic planarizing layer and forming and developing the second patterned resist, wherein the first patterned resist is a non-chemically amplified resist (n-CAR) or metal resist and the second patterned resist is CAR organic resist.

公开(公告)号：US20240153864A1

公开(公告)日：2024-05-09

申请号：US17980281

申请日：2022-11-03

Applicant: International Business Machines Corporation

Inventor： Koichi Motoyama ,  Chanro Park ,  Hsueh-Chung Chen ,  Yann Mignot

IPC: H01L23/522 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/088 ,  H01L27/092

CPC classification number: H01L23/5226 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/5283 ,  H01L27/0886 ,  H01L27/092

Abstract: A semiconductor structure includes a skip via disposed on a metal line of a first metallization layer, and a dielectric layer disposed on sidewalls of the skip via to define an opening. The dielectric layer has uniform sidewalls from an uppermost portion of the opening to a lowermost portion of the opening.

公开(公告)号：US11901440B2

公开(公告)日：2024-02-13

申请号：US17465316

申请日：2021-09-02

Applicant: International Business Machines Corporation

Inventor： Yann Mignot ,  Christopher J. Waskiewicz ,  Su Chen Fan ,  Brent Anderson ,  Junli Wang

IPC: H01L29/66 ,  H01L23/48 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L29/66795 ,  H01L21/823418 ,  H01L21/823431 ,  H01L23/481 ,  H01L29/0847 ,  H01L29/7851

Abstract: A semiconductor device containing a self-aligned contact rail is provided. The self-aligned contact rail can have a reduced critical dimension, CD. The self-aligned contact rail can be obtained utilizing a sacrificial semiconductor fin as a placeholder structure for the contact rail. The used of the sacrificial semiconductor fin enables reduced, and more controllable, CDs.

公开(公告)号：US11849647B2

公开(公告)日：2023-12-19

申请号：US17249521

申请日：2021-03-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tao Li ,  Yann Mignot ,  Ashim Dutta ,  Tsung-Sheng Kang ,  Wenyu Xu

IPC: H10N50/10 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10N50/80 ,  H10N50/01 ,  H10N50/10

Abstract: A semiconductor structure may include a magnetic tunnel junction layer on top and in electrical contact with a microstud, a hard mask layer on top of the magnetic tunnel junction layer, and a liner positioned along vertical sidewalls of the magnetic tunnel junction layer and vertical sidewalls of the hard mask layer. A top surface of the liner may be below a top surface of the hard mask layer. The semiconductor structure may include a spacer on top of the liner. The liner may separate the spacer from the magnetic tunnel junction layer and the hard mask layer. The semiconductor structure may include a first metal layer below and in electrical contact with the microstud and a second metal layer above the hard mask layer. A bottom portion of the second metal layer may surround a top portion of the hard mask layer.

公开(公告)号：US11688632B2

公开(公告)日：2023-06-27

申请号：US17136595

申请日：2020-12-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Alex Joseph Varghese ,  Marc A. Bergendahl ,  Andrew M. Greene ,  Dallas Lea ,  Matthew T. Shoudy ,  Yann Mignot ,  Ekmini A. De Silva ,  Gangadhara Raja Muthinti

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768

CPC classification number: H01L21/76829 ,  H01L21/7682 ,  H01L21/7688 ,  H01L21/76805 ,  H01L21/76844

Abstract: Semiconductor devices and methods for forming semiconductor devices include opening at least one contact via through a sacrificial material down to contacts. Sides of the at least one contact via are lined by selectively depositing a barrier on the sacrificial material, the barrier extending along sidewalls of the at least one contact via from a top surface of the sacrificial material down to a bottom surface of the sacrificial material proximal to the contacts such that the contacts remain exposed. A conductive material is deposited in the at least one contact via down to the contacts to form stacked contacts having the hard mask on sides thereof. The sacrificial material is removed.

公开(公告)号：US20230085494A1

公开(公告)日：2023-03-16

申请号：US17474292

申请日：2021-09-14

Applicant: International Business Machines Corporation

Inventor： Yann Mignot ,  YONGAN Xu ,  Hsueh-Chung Chen

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522

Abstract: Embodiments of the present invention are directed to fabrication methods and resulting structures having a back-end-of-line (BEOL) single damascene (SD) top via spacer defined by pillar mandrels. In a non-limiting embodiment of the invention, a first conductive line is formed in a first dielectric layer. A mandrel is formed over the first conductive line and a spacer is formed on a sidewall of the mandrel. A portion of a second dielectric layer is recessed to expose a top surface of the spacer and a top surface of the mandrel and the mandrel is removed. The spacer prevents damage to the second dielectric layer while removing the mandrel. The mandrel is replaced with a conductive material. A first portion of the conductive material defines a via and a second portion of the conductive material defines a second conductive line. The via couples the first conductive line to the second conductive line.

公开(公告)号：US20230070462A1

公开(公告)日：2023-03-09

申请号：US17470003

申请日：2021-09-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Injo Ok ,  Hsueh-Chung Chen ,  Mary Claire Silvestre ,  Yann Mignot

IPC: H01L45/00

Abstract: A semiconductor structure includes a plurality of conductive lines formed within a dielectric, wherein each of the plurality of conductive lines electrically communicates with a respective contact, a metal layer disposed over each of the plurality of conductive lines, a phase change memory (PCM) element disposed over the metal layer of each of the plurality of conductive lines, and a projection liner encapsulating the PCM element. Spacers directly contact sidewalls of the projection liner and the PCM element includes a GeSbTe (germanium-antimony-tellurium or GST) layer.

公开(公告)号：US20220302207A1

公开(公告)日：2022-09-22

申请号：US17205190

申请日：2021-03-18

Applicant: International Business Machines Corporation

Inventor： Yann Mignot ,  Oscar van der Straten ,  Dimitri Houssameddine

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/10 ,  H01L43/02

Abstract: A semiconductor device is provided. The semiconductor device includes a base layer, a first MRAM device formed on the base layer, and a second MRAM device formed on the base layer. The first MRAM device has a different performance characteristic than the second MRAM device.

公开(公告)号：US20220285606A1

公开(公告)日：2022-09-08

申请号：US17249521

申请日：2021-03-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tao Li ,  Yann Mignot ,  Ashim Dutta ,  Tsung-Sheng Kang ,  Wenyu Xu

IPC: H01L43/02 ,  H01L43/12

Abstract: A semiconductor structure may include a magnetic tunnel junction layer on top and in electrical contact with a microstud, a hard mask layer on top of the magnetic tunnel junction layer, and a liner positioned along vertical sidewalls of the magnetic tunnel junction layer and vertical sidewalls of the hard mask layer. A top surface of the liner may be below a top surface of the hard mask layer. The semiconductor structure may include a spacer on top of the liner. The liner may separate the spacer from the magnetic tunnel junction layer and the hard mask layer. The semiconductor structure may include a first metal layer below and in electrical contact with the microstud and a second metal layer above the hard mask layer. A bottom portion of the second metal layer may surround a top portion of the hard mask layer.

公开(公告)号：US11424367B2

公开(公告)日：2022-08-23

申请号：US17124458

申请日：2020-12-16

Applicant: International Business Machines Corporation

Inventor： Eric Miller ,  Julien Frougier ,  Yann Mignot ,  Andrew M. Greene

IPC: H01L29/775 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/66

Abstract: A conformally deposited metal liner used for forming discrete, wrap-around contact structures is localized between pairs of gate structures and below the tops of the gate structures. Block mask patterning is employed to protect transistors over active regions of a substrate while portions of the metal liner between active regions are removed. A chamfering technique is employed to selectively remove further portions of the metal liner within the active regions. Metal silicide liners formed on the source/drain regions using the conformally deposited metal liner are electrically connected to source/drain contact metal following the deposition and patterning of a dielectric layer and subsequent metallization.