公开(公告)号：US10580882B2

公开(公告)日：2020-03-03

申请号：US15770628

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Jack T. Kavalieros ,  Willy Rachmady ,  Matthew V. Metz ,  Van H. Le ,  Seiyon Kim ,  Benjamin Chu-Kung

IPC: H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/267 ,  H01L29/06 ,  H01L29/08 ,  H01L29/51

Abstract: Embodiments of the present invention are directed to low band gap channel semiconductor devices. In an example, a device includes a first semiconductor material formed above a substrate, the first semiconductor material having a first band gap. A gate dielectric layer is on a surface of the first semiconductor material. A gate electrode is on the gate dielectric layer. A pair of source/drain regions is on opposite sides of the gate electrode. A channel is disposed in the first semiconductor material between the pair of source/drain regions and beneath the gate electrode. The pair of source/drain regions includes a second semiconductor material having a second band gap, and a third semiconductor material having a third band gap. The second semiconductor material is between the first semiconductor material and the third semiconductor material, and the second band gap is greater than the first bandgap.

公开(公告)号：US20190341453A1

公开(公告)日：2019-11-07

申请号：US16465758

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Seung Hoon Sung ,  Dipanjan Basu ,  Glenn A. Glass ,  Harold W. Kennel ,  Ashish Agrawal ,  Benjamin Chu-Kung ,  Anand S. Murthy ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/167 ,  H01L21/02

Abstract: An apparatus is provided which comprises: a semiconductor region on a substrate, a gate stack on the semiconductor region, a source region of doped semiconductor material on the substrate adjacent a first side of the semiconductor region, a drain region of doped semiconductor material on the substrate adjacent a second side of the semiconductor region, and a transition region in the drain region, adjacent the semiconductor region, wherein the transition region comprises varying dopant concentrations that increase in a direction away from the semiconductor region. Other embodiments are also disclosed and claimed.

公开(公告)号：US20190305137A1

公开(公告)日：2019-10-03

申请号：US15938153

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Van H. Le ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Shriram Shivaraman ,  Benjamin Chu-Kung ,  Yih Wang ,  Tahir Ghani

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/08 ,  H01L29/04 ,  H01L27/108 ,  H01L29/66 ,  H01L29/10 ,  H01L21/02

Abstract: Disclosed herein are dual gate trench shaped thin film transistors and related methods and devices. Exemplary thin film transistor structures include a non-planar semiconductor material layer having a first portion extending laterally over a first gate dielectric layer, which is over a first gate electrode structure, and a second portion extending along a trench over the first gate dielectric layer, a second gate electrode structure at least partially within the trench, and a second gate dielectric layer between the second gate electrode structure and the first portion.

公开(公告)号：US20190305101A1

公开(公告)日：2019-10-03

申请号：US15939081

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Van H. Le ,  Sean T. Ma ,  Jack Kavalieros ,  Benjamin Chu-Kung

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: Techniques and mechanisms for improved performance characteristics of a transistor device. In an embodiment, a transistor of an integrated circuit comprises a source, a drain, a gate, a gate dielectric and a semiconductor structure which adjoins the gate dielectric. The semiconductor structure is configured to provide a conductive channel between the source and drain. The semiconductor structure includes first, second and third portions, the second portion between the source and the gate, and the third portion between the drain and the gate, wherein the first portion connects the second portion and third portion to one another. A thickness of the first portion is less than another thickness of one of the second portion or the third portion. In another embodiment, the locations of thicker portions of semiconductor structure mitigate overall transistor capacitance, while a thinner intermediary portion of the semiconductor structure promotes good sub-threshold swing characteristics.

公开(公告)号：US10249742B2

公开(公告)日：2019-04-02

申请号：US15576468

申请日：2015-06-27

Applicant: Intel Corporation

Inventor： Van H. Le ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Ashish Agrawal ,  Matthew V. Metz ,  Willy Rachmady ,  Marc C. French ,  Jack T. Kavalieros ,  Rafael Rios ,  Seiyon Kim ,  Seung Hoon Sung ,  Sanaz K. Gardner ,  James M. Powers ,  Sherry R. Taft

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L29/10

Abstract: A method including forming a non-planar conducting channel of a device between junction regions on a substrate, the substrate including a blocking material beneath the channel, the blocking material including a property to inhibit carrier leakage; and forming a gate stack on the channel, the gate stack including a dielectric material and a gate electrode. A method including forming a buffer material on a semiconductor substrate, the buffer material including a semiconductor material including a different lattice structure than the substrate; forming a blocking material on the buffer material, the blocking material including a property to inhibit carrier leakage; and forming a transistor device on the substrate. An apparatus including a non-planar multi-gate device on a substrate including a transistor device including a channel disposed on a substrate including a blocking material beneath the channel, the blocking material including a property to inhibit carrier leakage.

公开(公告)号：US10204989B2

公开(公告)日：2019-02-12

申请号：US15598290

申请日：2017-05-17

Applicant: Intel Corporation

Inventor： Benjamin Chu-Kung ,  Sherry R. Taft ,  Van H. Le ,  Sansaptak Dasgupta ,  Seung Hoon Sung ,  Sanaz K. Gardner ,  Matthew V. Metz ,  Marko Radosavljevic ,  Han Wui Then

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/06 ,  H01L29/20 ,  H01L29/161 ,  H01L29/78 ,  H01L21/02

Abstract: Techniques are disclosed for forming a defect-free semiconductor structure on a dissimilar substrate with a multi-aspect ratio mask. The multi-aspect ratio mask comprises a first, second, and third layer formed on a substrate. The second layer has a second opening wider than a first opening and a third opening in the first and third layers, respectively. All three openings are centered along a common central axis. A semiconductor material is grown from the top surface of the substrate and laterally onto the top surface of the first layer within the second opening. The semiconductor material disposed within and vertically below the third opening is etched by using the third layer as an etch mask so that the remaining material that laterally overflowed onto the top surface of the first layer forms a remaining structure.

公开(公告)号：US10186581B2

公开(公告)日：2019-01-22

申请号：US15623165

申请日：2017-06-14

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

IPC: H01L29/15 ,  H01L29/04 ,  H01L27/088 ,  H01L29/66 ,  H01L29/775 ,  H01L29/778 ,  H01L29/06 ,  H01L29/20 ,  H01L29/786 ,  H01L29/78 ,  B82Y10/00 ,  H01L23/66 ,  H01L27/06 ,  H01L29/205 ,  H01L29/423 ,  H01L21/02

Abstract: A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.

公开(公告)号：US10026845B2

公开(公告)日：2018-07-17

申请号：US15465448

申请日：2017-03-21

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Willy Rachmady ,  Van H. Le ,  Seung Hoon Sung ,  Jessica S. Kachian ,  Jack T. Kavalieros ,  Han Wui Then ,  Gilbert Dewey ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Niloy Mukherjee

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/165 ,  H01L29/06 ,  H01L29/205 ,  H01L29/423 ,  H01L29/78

Abstract: Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.

公开(公告)号：US10020371B2

公开(公告)日：2018-07-10

申请号：US15252125

申请日：2016-08-30

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Willy Rachmady ,  Van H. Le ,  Gilbert Dewey ,  Niloy Mukherjee ,  Matthew V. Metz ,  Han Wui Then ,  Marko Radosavljevic

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L23/485 ,  H01L29/66 ,  H01L29/775 ,  G11C7/02 ,  H01L23/535 ,  H01L27/115 ,  H01L29/16 ,  H01L29/78 ,  B82Y99/00 ,  B82Y40/00

CPC classification number: H01L29/41791 ,  B82Y40/00 ,  B82Y99/00 ,  G11C7/02 ,  H01L23/485 ,  H01L23/535 ,  H01L27/115 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696 ,  H01L2029/7858 ,  H01L2924/0002 ,  Y10S977/762 ,  Y10S977/89 ,  H01L2924/00

Abstract: Embodiments of the present disclosure provide contact techniques and configurations for reducing parasitic resistance in nanowire transistors. In one embodiment, an apparatus includes a semiconductor substrate, an isolation layer formed on the semiconductor substrate, a channel layer including nanowire material formed on the isolation layer to provide a channel for a transistor, and a contact coupled with the channel layer, the contact being configured to surround, in at least one planar dimension, nanowire material of the channel layer and to provide a source terminal or drain terminal for the transistor.

公开(公告)号：US09806203B2

公开(公告)日：2017-10-31

申请号：US15178391

申请日：2016-06-09

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Sansaptak Dasgupta ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Sanaz K. Gardner ,  Robert S. Chau

IPC: H01L29/20 ,  H01L29/78 ,  H01L29/786 ,  H01L29/772 ,  H01L29/66 ,  H01L21/02 ,  H01L29/423 ,  H01L29/04 ,  H01L29/06 ,  H01L29/205

CPC classification number: H01L29/78696 ,  H01L21/02387 ,  H01L21/02389 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0251 ,  H01L21/02538 ,  H01L21/0254 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66409 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/772 ,  H01L29/785 ,  H01L29/78681

Abstract: A III-N semiconductor channel is compositionally graded between a transition layer and a III-N polarization layer. In embodiments, a gate stack is deposited over sidewalls of a fin including the graded III-N semiconductor channel allowing for formation of a transport channel in the III-N semiconductor channel adjacent to at least both sidewall surfaces in response to a gate bias voltage. In embodiments, a gate stack is deposited completely around a nanowire including a III-N semiconductor channel compositionally graded to enable formation of a transport channel in the III-N semiconductor channel adjacent to both the polarization layer and the transition layer in response to a gate bias voltage.