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342 条记录 (耗时 0.043 秒)

    System and method for decoding commands based on command signals and operating state
    91.
    发明授权
    System and method for decoding commands based on command signals and operating state 有权
    基于命令信号和操作状态对命令进行解码的系统和方法

    公开(公告)号：US07757061B2

    公开(公告)日：2010-07-13

    申请号：US11121868

    申请日：2005-05-03

    申请人： Jeffery W. Janzen ,  Brent Keeth ,  Jeffrey P. Wright ,  James S. Cullum

    发明人： Jeffery W. Janzen ,  Brent Keeth ,  Jeffrey P. Wright ,  James S. Cullum

    IPC分类号： G06F13/36

    CPC分类号： G11C11/4096 ,  G11C7/1072 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091

    摘要： A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. A command is selected from a first set of operations according to the command signals when the memory system is in a first operating state and a command is selected from a second set of operations according to the command signals when the memory system is in a second operating state.

    摘要翻译： 一种用于对命令信号进行解码的系统和方法，该系统和方法包括一个命令解码器，该命令解码器经配置以产​​生内部控制信号，以根据命令信号和操作状态执行操作。 命令信号的相同组合可以根据操作状态请求不同的命令。 当存储器系统处于第一操作状态时，根据命令信号从第一组操作中选择命令，并且当存储器系统处于第二操作时根据命令信号从第二组操作中选择命令 州。

    Apparatus and method for repairing a semiconductor memory
    93.
    发明授权
    Apparatus and method for repairing a semiconductor memory 有权
    用于修复半导体存储器的装置和方法

    公开(公告)号：US07492652B2

    公开(公告)日：2009-02-17

    申请号：US11876477

    申请日：2007-10-22

    申请人： Chris G. Martin ,  Troy A. Manning ,  Brent Keeth

    发明人： Chris G. Martin ,  Troy A. Manning ,  Brent Keeth

    IPC分类号： G11C7/00

    CPC分类号： G11C17/165 ,  G11C29/4401 ,  G11C29/789 ,  G11C29/802 ,  G11C29/808 ,  G11C2029/4402

    摘要： An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores a first cached address corresponding to the first address designating the at least one defective memory cell. The repair circuit distributes the first address designating the at least one defective memory cell of the first memory cell array to the first volatile cache. Match circuitry substitutes at least one redundant memory cell from the first redundant cell array for the at least one defective memory cell in the first memory cell array when a first memory access corresponds to the first cached address.

    摘要翻译： 用于修复半导体存储器件的装置和方法包括：第一存储单元阵列，第一冗余单元阵列和修复电路，被配置为在第一存储单元阵列中非易失性地存储指定至少一个有缺陷的存储单元的第一地址。 第一易失性高速缓存存储对应于指定所述至少一个有缺陷的存储器单元的第一地址的第一高速缓存地址。 修复电路将指定第一存储单元阵列的至少一个缺陷存储单元的第一地址分配给第一易失性高速缓存。 当第一存储器访问对应于第一缓存地址时，匹配电路将来自第一冗余单元阵列的至少一个冗余存储单元替换为第一存储单元阵列中的至少一个有缺陷的存储单元。

    Method and system for using dynamic random access memory as cache memory
    94.
    发明申请
    Method and system for using dynamic random access memory as cache memory 有权
    使用动态随机存取存储器作为高速缓冲存储器的方法和系统

    公开(公告)号：US20080177943A1

    公开(公告)日：2008-07-24

    申请号：US12069812

    申请日：2008-02-12

    申请人： Brent Keeth ,  Brian M. Shirley ,  Charles H. Dennison ,  Kevin J. Ryan

    发明人： Brent Keeth ,  Brian M. Shirley ,  Charles H. Dennison ,  Kevin J. Ryan

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0893 ,  G06F12/0846 ,  G06F12/0897 ,  G11C7/1006 ,  G11C7/1042 ,  G11C11/406 ,  G11C11/409 ,  G11C15/043

    摘要： A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.

    摘要翻译： 高速缓冲存储器系统和方法包括具有多个存储体的DRAM，并且它们还包括两个SRAM，每个SRAM的容量等于DRAM的每个存储体的容量。 在操作中，从DRAM的存储体读出的数据被存储在一个SRAM中，从而通过从SRAM读取来缓存对该存储体的重复命中。 在写入正在刷新的存储体的情况下，写入数据被存储在一个SRAM中。 在银行刷新完成之后，存储在SRAM中的数据被传送到DRAM存储体。 在从SRAM到DRAM的数据传输期间经历刷新并发生的第二DRAM组的后续读或写存储在第二存储体或其它SRAM中。

    Method and apparatus for data compression in memory devices
    97.
    发明授权
    Method and apparatus for data compression in memory devices 有权
    用于存储器件中的数据压缩的方法和装置

    公开(公告)号：US07190625B2

    公开(公告)日：2007-03-13

    申请号：US11217618

    申请日：2005-08-31

    申请人： Brent Keeth

    发明人： Brent Keeth

    IPC分类号： G11C7/00

    CPC分类号： G11C29/1201 ,  G11C29/40

    摘要： A test circuit for a memory device having a pair of arrays each of which includes a plurality of memory cells arranged in rows and columns. A pair of complementary digit lines is provided for each column of each array. The digit lines are selectively coupled to a pair of I/O lines for each array which are, in turn, coupled to a pair of complementary data lines. The data lines are coupled to respective inputs of a DC sense amplifier, one of which is provided for each array. A multiplexer connects the pair of I/O lines for either one of the arrays to the data lines in a normal operating mode. Thus, in the normal operating mode, data are selectively coupled to the inputs of the DC sense amplifier from the complementary digit lines for an addressed column. In a test mode, the multiplexer connects the I/O lines for both arrays to the data lines to compress the data from the two arrays. Combinatorial logic then determines if both of the data lines have the same logical value, indicating disagreement between the data from the memory arrays that may indicate the presence of a defective memory cell in one or the other array. Thus, in the test mode, data are simultaneously coupled to the inputs of the DC sense amplifier from respective digit lines coupled to two different memory cells, thereby increasing the rate at which background data that has been written to the arrays can be read from the arrays.

    摘要翻译： 一种用于具有一对阵列的存储器件的测试电路，每个阵列包括以行和列排列的多个存储器单元。 为每个阵列的每列提供一对补码数字线。 数字线选择性地耦合到每个阵列的一对I / O线，这些I / O线又耦合到一对补充数据线。 数据线耦合到DC读出放大器的相应输入端，其中之一为每个阵列提供。 一个多路复用器将正常操作模式中的一个阵列的一对I / O线连接到数据线。 因此，在正常操作模式中，数据从针对寻址列的互补数字线选择性地耦合到DC读出放大器的输入。 在测试模式下，多路复用器将两个阵列的I / O线连接到数据线，以压缩来自两个阵列的数据。 组合逻辑然后确定两条数据线是否具有相同的逻辑值，表示来自存储器阵列的数据之间的不一致，可能指示在一个或另一个阵列中存在有缺陷的存储器单元。 因此，在测试模式中，数据同时从耦合到两个不同存储单元的各个数字线耦合到DC读出放大器的输入端，由此增加已写入阵列的背景数据可以从 阵列