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105 条记录 (耗时 0.035 秒)

    Method of forming high voltage N-LDMOS transistors having shallow trench isolation region with drain extensions
    91.
    发明授权
    Method of forming high voltage N-LDMOS transistors having shallow trench isolation region with drain extensions 失效
    形成具有漏极延伸的浅沟槽隔离区的高电压N-LDMOS晶体管的方法

    公开(公告)号：US07297582B2

    公开(公告)日：2007-11-20

    申请号：US10991936

    申请日：2004-11-18

    申请人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  William R. Tonti

    IPC分类号： H01L21/336

    CPC分类号： H01L29/0878 ,  H01L21/26586 ,  H01L21/266 ,  H01L29/0653 ,  H01L29/086 ,  H01L29/42368 ,  H01L29/66689 ,  H01L29/7816

    摘要： A method and structure is disclosed for a transistor having a gate, a channel region below the gate, a source region on one side of the channel region, a drain region on an opposite side of the channel region from the source region, a shallow trench isolation (STI) region in the substrate between the drain region and the channel region, and a drain extension below the STI region. The drain extension is positioned along a bottom of the STI region and along a portion of sides of the STI. Portions of the drain extension along the bottom of the STI may comprise different dopant implants than the portions of the drain extensions along the sides of the STI. Portions of the drain extensions along sides of the STI extend from the bottom of the STI to a position partially up the sides of the STI. The STI region is below a portion of the gate. The drain extension provides a conductive path between the drain region and the channel region around a lower perimeter of the STI. The drain region is positioned further from the gate than the source region.

    摘要翻译： 公开了一种用于晶体管的方法和结构，该晶体管具有栅极，栅极下方的沟道区，沟道区一侧的源极区，与源极区沟道区相反侧的漏极区，浅沟槽 在漏极区和沟道区之间的衬底中的隔离（STI）区，以及在STI区之下的漏极延伸。 漏极延伸沿着STI区域的底部并沿着STI的边的一部分定位。 沿着STI底部的漏极延伸部分可以包括不同于沿着STI侧面的漏极延伸部分的掺杂剂注入。 沿着STI侧面的排水延伸部分从STI的底部延伸到部分沿着STI侧面的位置。 STI区域位于栅极的一部分之下。 漏极延伸部在漏极区域和围绕STI的下周边的沟道区域之间提供导电路径。 漏极区域比源极区域更靠近栅极定位。

    Device and method for using a lessened load to measure signal skew at the output of an integrated circuit
    92.
    发明授权
    Device and method for using a lessened load to measure signal skew at the output of an integrated circuit 有权
    使用减轻负载来测量集成电路输出端的信号偏移的装置和方法

    公开(公告)号：US07219270B1

    公开(公告)日：2007-05-15

    申请号：US10719878

    申请日：2003-11-21

    申请人： Jeffrey S. Brown ,  Craig R. Chafin

    发明人： Jeffrey S. Brown ,  Craig R. Chafin

    IPC分类号： G11B20/20

    CPC分类号： G11B20/1816 ,  G01R31/31708 ,  G01R31/31725 ,  G11B20/182

    摘要： A device and method are provided for testing the timing of an output signal from a circuit. The output signal can be sent from a circuit contained within a portion of an integrated circuit, and represents a response to a test pattern or stimuli applied to that circuit. The output signal is compared to an expected output signal to determine skew of that signal relative to the clocking of the circuit. Testing the output signal involves placing a characterization path within the functional path of the output signal, between the circuits being tested and an output terminal that can receive a measurement device. By placing the characterization path into the functional path, the output signal sees only a single load gate terminal of, for example, a logic gate. The reduced loading not only positively impacts the normal operation of the output signal, but also beneficially minimizes the possibility of any inaccuracies in the characterization testing.

    摘要翻译： 提供了一种用于测试来自电路的输出信号的定时的装置和方法。 输出信号可以从包含在集成电路的一部分内的电路发送，并且表示对应用于该电路的测试图案或刺激的响应。 将输出信号与期望的输出信号进行比较，以确定该信号相对于电路的时钟脉冲。 测试输出信号涉及将表征路径放置在输出信号的功能路径之间，正在测试的电路和可接收测量设备的输出端子之间。 通过将表征路径放置到功能路径中，输出信号仅看到例如逻辑门的单个负载门极。 减少负载不仅对输出信号的正常运行产生积极影响，而且有利地最小化了特性测试中任何不准确的可能性。

    DRAM cell with enhanced SER immunity
    93.
    发明授权
    DRAM cell with enhanced SER immunity 失效
    具有增强的SER免疫力的DRAM单元

    公开(公告)号：US06888187B2

    公开(公告)日：2005-05-03

    申请号：US10064869

    申请日：2002-08-26

    申请人： Jeffrey S. Brown ,  David M. Fried ,  Edward J. Nowak ,  Beth Ann Rainey

    发明人： Jeffrey S. Brown ,  David M. Fried ,  Edward J. Nowak ,  Beth Ann Rainey

    IPC分类号： H01L27/108 ,  H01L21/02 ,  H01L21/336 ,  H01L21/8242 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC分类号： H01L27/108 ,  H01L27/10873 ,  H01L28/90 ,  H01L29/785

    摘要： A memory cell that has first and second fully depleted transfer devices each having a body region and first and second diffused electrodes. The cell has a differential storage capacitor having at least one node abutting and in electrical contact with one of the first and second diffused electrodes of each of the transfer devices. The storage capacitor has a primary capacitance and a plurality of inherent capacitances, wherein the primary capacitance has a capaictive value that is at least approximately five times greater than that of the plurality of inherent capacitances.

    摘要翻译： 具有第一和第二完全耗尽的转移装置的存储器单元，每个具有体区和第一和第二扩散电极。 电池具有差分存储电容器，其具有至少一个节点邻接并与每个转移装置的第一和第二扩散电极之一电接触。 存储电容器具有初级电容和多个固有电容，其中初级电容具有比多个固有电容的至少大约五倍的电容值。

    Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure
    95.
    发明授权
    Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure 失效
    基于相同测试结构的半导体应力诱发缺陷和反熔丝的测试结构和方法

    公开(公告)号：US06770907B2

    公开(公告)日：2004-08-03

    申请号：US10449426

    申请日：2003-05-30

    申请人： Wagdi W. Abadeer ,  Eric Adler ,  Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Jonathan M. McKenna ,  Jed H. Rankin ,  Edward W. Sengle ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Eric Adler ,  Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Jonathan M. McKenna ,  Jed H. Rankin ,  Edward W. Sengle ,  William R. Tonti

    IPC分类号： H01L2358

    CPC分类号： H01L22/34 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for detecting semiconductor process stress-induced defects. The method comprising: providing a polysilicon-bounded test diode, the diode comprising a diffused first region within an upper portion of a second region of a silicon substrate, the second region of an opposite dopant type from the first region, the first region surrounded by a peripheral dielectric isolation, a peripheral polysilicon gate comprising a polysilicon layer over a dielectric layer and the gate overlapping a peripheral portion of the first region; stressing the diode; and monitoring the stressed diode for spikes in gate current during the stress, determining the frequency distribution of the slope of the forward bias voltage versus the first region current at the pre-selected forward bias voltage and monitoring, after stress, the diode for soft breakdown. A DRAM cell may be substituted for the diode. The use of the diode as an antifuse is also disclosed.

    摘要翻译： 一种检测半导体工艺应力诱发缺陷的方法。 该方法包括：提供多晶硅界限的测试二极管，二极管包括在硅衬底的第二区域的上部内的扩散的第一区域，与第一区域相反的掺杂剂类型的第二区域，第一区域由 外围电介质隔离，外围多晶硅栅极，包括介电层上的多晶硅层，栅极与第一区域的周边部分重叠; 强调二极管; 并且在应力期间监视施加二极管的栅极电流尖峰，确定正向偏置电压的斜率与预先选择的正向偏置电压下的第一区域电流的频率分布，并且在应力之后监视用于软击穿的二极管 。 DRAM单元可以代替二极管。 还公开了使用二极管作为反熔丝。

    Method for producing a polysilicon circuit element
    98.
    发明授权
    Method for producing a polysilicon circuit element 失效
    多晶硅电路元件的制造方法

    公开(公告)号：US06429066B1

    公开(公告)日：2002-08-06

    申请号：US09465097

    申请日：1999-12-16

    申请人： Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Steven H. Voldman

    发明人： Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Steven H. Voldman

    IPC分类号： H01L218242

    CPC分类号： H01L29/66181 ,  H01L21/76237 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/823842 ,  H01L21/82385 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/94 ,  Y10S257/907

    摘要： A circuit element comprising a semiconductor substrate. A well region of a first conductivity type is formed in a surface of the substrate. A dielectric film is formed on the substrate. A gate conductor of the first conductivity type is formed on the dielectric film over the well region of the substrate. The gate conductor is formed of a polycrystalline silicon film. The gate conductor has an impurity concentration substantially lower than a standard impurity concentration for the gate conductor of an MOS device. A polycrystalline silicon edge spacer is formed on each side of the gate conductor. A first pair of first conductivity type impurity diffusion regions are formed adjacent to the polycrystalline silicon edge spacers. The polycrystalline silicon film and edge spacers lie on a portion of the substrate between the first pair of first conductivity type impurity diffusion regions. The first pair of first conductivity type impurity diffusion regions have an impurity concentration substantially lower than the standard impurity concentration for the gate conductor of an MOS device. The gate conductor and the first pair of first conductivity type impurity diffusion regions may be formed by a single implantation step. Applications include ESD protection, analog applications, peripheral input/output circuitry, decoupling capacitors, and resistor ballasting.

    摘要翻译： 一种包括半导体衬底的电路元件。 第一导电类型的阱区形成在衬底的表面中。 在基板上形成电介质膜。 在衬底的阱区上的电介质膜上形成第一导电类型的栅极导体。 栅极导体由多晶硅膜形成。 栅极导体的杂质浓度基本上低于MOS器件的栅极导体的标准杂质浓度。 在栅极导体的每一侧上形成多晶硅边缘隔离物。 第一对第一导电型杂质扩散区形成在与多晶硅边缘隔离物相邻的位置。 多晶硅膜和边缘隔离物位于第一对第一导电型杂质扩散区之间的衬底的一部分上。 第一对第一导电型杂质扩散区的杂质浓度基本上低于MOS器件的栅极导体的标准杂质浓度。 可以通过单个注入步骤形成栅极导体和第一对第一导电型杂质扩散区。 应用包括ESD保护，模拟应用，外围输入/输出电路，去耦电容和电阻镇流器。

    Method for forming transistors with raised source and drains and device formed thereby
    100.
    发明授权
    Method for forming transistors with raised source and drains and device formed thereby 有权
    用于形成具有升高的源极和漏极的晶体管的方法以及由此形成的器件

    公开(公告)号：US06255178B1

    公开(公告)日：2001-07-03

    申请号：US09368767

    申请日：1999-08-05

    申请人： Jeffrey S. Brown ,  James S. Dunn ,  Steven J. Holmes ,  David V. Horak ,  Robert K. Leidy ,  Steven H. Voldman

    发明人： Jeffrey S. Brown ,  James S. Dunn ,  Steven J. Holmes ,  David V. Horak ,  Robert K. Leidy ,  Steven H. Voldman

    IPC分类号： H01L21336

    CPC分类号： H01L29/66492 ,  G03F7/095 ,  G03F7/38 ,  H01L21/0274 ,  H01L21/26586 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/6659

    摘要： The preferred embodiment of the present invention provides a transistor structure and method for fabricating the same that overcomes the disadvantages of the prior art. In particular, the preferred structure and method results in lower leakage and junction capacitance by using raised source and drains which are partially isolated from the substrate by a dielectric layer. The raised source and drains are preferably fabricated from the same material layer used to form the transistor gate. The preferred method for fabricating the transistor uses hybrid resist to accurately pattern the gate material layer into regions for the gate, the source and the drain. The source and drain regions are then connected to the substrate by growing silicon. The preferred method thus results in an improved transistor structure while not requiring excessive fabrication steps.

    摘要翻译： 本发明的优选实施例提供了克服现有技术的缺点的晶体管结构及其制造方法。 特别地，优选的结构和方法通过使用通过电介质层与衬底部分隔离的凸起源极和漏极导致较低的漏电和结电容。 升高的源极和漏极优选由用于形成晶体管栅极的相同材料层制成。 用于制造晶体管的优选方法使用混合抗蚀剂将栅极材料层精确地图案化成用于栅极，源极和漏极的区域。 然后通过生长硅将源极区和漏极区连接到衬底。 因此，优选的方法导致改进的晶体管结构，而不需要过多的制造步骤。