公开(公告)号：US08435864B2

公开(公告)日：2013-05-07

申请号：US13432440

申请日：2012-03-28

申请人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Keith E. Downes ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert M. Rassel ,  Anthony K. Stamper

发明人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Keith E. Downes ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert M. Rassel ,  Anthony K. Stamper

IPC分类号： H01L21/28

CPC分类号： H01L21/32139 ,  H01L21/32136 ,  H01L28/75

摘要： A method of fabricating a MIM capacitor is provided. The method includes providing a substrate including a dielectric layer formed on a first conductive layer and a second conductive layer formed over the dielectric layer, and patterning a mask on the second conductive layer. Exposed portions of the second conductive layer are removed to form an upper plate of a MIM capacitor having edges substantially aligned with respective edges of the mask. The upper plate is undercut so that edges of the upper plate are located under the mask. Exposed portions of the dielectric layer and the first conductive layer are removed using the mask to form a capacitor dielectric layer and a lower plate of the MIM capacitor having edges substantially aligned with respective edges of the mask.

摘要翻译： 提供一种制造MIM电容器的方法。 该方法包括提供包括形成在第一导电层上的电介质层和形成在电介质层上的第二导电层的衬底，以及在第二导电层上构图掩模。 去除第二导电层的暴露部分以形成具有与掩模的相应边缘基本对齐的边缘的MIM电容器的上板。 上板被切下，使得上板的边缘位于掩模下方。 使用掩模去除电介质层和第一导电层的暴露部分，以形成MIM电容器的电容器电介质层和具有基本上与掩模的各个边缘对准的边缘的MIM电容器的下板。

公开(公告)号：US08338265B2

公开(公告)日：2012-12-25

申请号：US12269069

申请日：2008-11-12

申请人： Douglas D. Coolbaugh ,  Jeffrey B. Johnson ,  Peter J. Lindgren ,  Xuefeng Liu ,  James S. Nakos ,  Bradley A. Orner ,  Robert M. Rassel ,  David C. Sheridan

发明人： Douglas D. Coolbaugh ,  Jeffrey B. Johnson ,  Peter J. Lindgren ,  Xuefeng Liu ,  James S. Nakos ,  Bradley A. Orner ,  Robert M. Rassel ,  David C. Sheridan

IPC分类号： H01L21/76

CPC分类号： H01L21/743 ,  H01L21/28518 ,  H01L21/76224 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/41 ,  H01L2924/0002 ,  H01L2924/00

摘要： A trench contact silicide is formed on an inner wall of a contact trench that reaches to a buried conductive layer in a semiconductor substrate to reduce parasitic resistance of a reachthrough structure. The trench contact silicide is formed at the bottom, on the sidewalls of the trench, and on a portion of the top surface of the semiconductor substrate. The trench is subsequently filled with a middle-of-line (MOL) dielectric. A contact via may be formed on the trench contact silicide. The trench contact silicide may be formed through a single silicidation reaction with a metal layer or through multiple silicidation reactions with multiple metal layers.

摘要翻译： 沟槽接触硅化物形成在接触沟槽的内壁上，该接触沟槽的内壁到达半导体衬底中的掩埋导电层，以减小通孔结构的寄生电阻。 沟槽接触硅化物形成在底部，沟槽的侧壁上以及在半导体衬底的顶表面的一部分上。 沟槽随后填充有中间线（MOL）电介质。 可以在沟槽接触硅化物上形成接触通孔。 沟槽接触硅化物可以通过与金属层的单一硅化反应或通过与多个金属层的多次硅化反应形成。

公开(公告)号：US08299475B2

公开(公告)日：2012-10-30

申请号：US13408141

申请日：2012-02-29

申请人： Jeffrey P. Gambino ,  Zhong-Xiang He ,  Kevin N. Ogg ,  Richard J. Rassel ,  Robert M. Rassel

发明人： Jeffrey P. Gambino ,  Zhong-Xiang He ,  Kevin N. Ogg ,  Richard J. Rassel ,  Robert M. Rassel

IPC分类号： H01L27/15 ,  H01L29/267 ,  H01L31/12 ,  H01L33/00 ,  G06F17/50

CPC分类号： H01L27/14623 ,  H01L27/14609 ,  H01L27/14632 ,  H01L27/14643

摘要： A CMOS image sensor pixel includes a conductive light shield, which is located between a first dielectric layer and a second dielectric layer. At least one via extends from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer is formed in the metal interconnect structure. The conductive light shield may be formed within a contact level between a top surface of a semiconductor substrate and a first metal line level, or may be formed in any metal interconnect via level between two metal line levels. The inventive CMOS image sensor pixel enables reduction of noise in the signal stored in the floating drain.

摘要翻译： CMOS图像传感器像素包括位于第一介电层和第二介电层之间的导电屏蔽。 在金属互连结构中形成有至少一个通孔从第二电介质层的顶表面延伸到第一介电层的底表面。 导电屏蔽可以形成在半导体衬底的顶表面和第一金属线电平之间的接触电平内，或者可以通过两个金属线电平之间的电平形成在任何金属互连中。 本发明的CMOS图像传感器像素能够减少存储在浮动漏极中的信号中的噪声。

公开(公告)号：US20120193747A1

公开(公告)日：2012-08-02

申请号：US13019716

申请日：2011-02-02

申请人： Robert M. Rassel ,  Mark E. Stidham

发明人： Robert M. Rassel ,  Mark E. Stidham

IPC分类号： H01L29/872 ,  G06F17/50 ,  H01L21/329

CPC分类号： H01L29/66143 ,  G06F17/5068 ,  H01L29/872

摘要： Disclosed are embodiments of a Schottky barrier diode. This diode can be formed in a semiconductor substrate having a doped region with a first conductivity type. A trench isolation structure can laterally surround a section of the doped region at the top surface of the substrate. A semiconductor layer can be positioned on the top surface of the substrate. This semiconductor layer can have a Schottky barrier portion over the defined section of the doped region and a guardring portion over the trench isolation structure laterally surrounding the Schottky barrier portion. The Schottky barrier portion can have the first conductivity type and the guarding portion can have a second conductivity type different from the first conductivity type. A metal silicide layer can overlie the semiconductor layer. Also disclosed are embodiments of a method of forming this Schottky barrier diode and of a design structure for the Schottky barrier diode.

摘要翻译： 公开了肖特基势垒二极管的实施例。 该二极管可以形成在具有第一导电类型的掺杂区域的半导体衬底中。 沟槽隔离结构可以横向围绕衬底顶表面处的掺杂区域的一部分。 半导体层可以位于衬底的顶表面上。 该半导体层可以在掺杂区域的限定部分上方具有肖特基势垒部分，并且在沟槽隔离结构之上的护套部分横向围绕肖特基势垒部分。 肖特基势垒部分可以具有第一导电类型，并且防护部分可以具有不同于第一导电类型的第二导电类型。 金属硅化物层可以覆盖半导体层。 还公开了形成该肖特基势垒二极管的方法和肖特基势垒二极管的设计结构的实施例。

公开(公告)号：US20120181700A1

公开(公告)日：2012-07-19

申请号：US13005883

申请日：2011-01-13

申请人： Jeffrey P. Bonn ,  Brent A. Goplen ,  Brian L. Kinsman ,  Robert M. Rassel ,  Edmund J. Sprogis ,  Daniel S. Vanslette

发明人： Jeffrey P. Bonn ,  Brent A. Goplen ,  Brian L. Kinsman ,  Robert M. Rassel ,  Edmund J. Sprogis ,  Daniel S. Vanslette

IPC分类号： H01L23/48 ,  G06F17/50

CPC分类号： H01L21/76898 ,  G06F17/5068 ,  G06F2217/80 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the invention provide an integrated circuit (IC) having reduced through silicon via (TSV)-induced stresses and related IC design structures and methods. In one embodiment, the invention includes a method of designing an integrated circuit (IC) having reduced substrate stress, the method including: placing in an IC design file a plurality of through silicon via (TSV) placeholder cells, each placeholder cell having an undefined TSV orientation; replacing a first portion of the plurality of TSV placeholder cells with a first group of TSV cells having a first orientation; and replacing a second portion of the plurality of TSV placeholder cells with a second group of TSV cells having a second orientation substantially perpendicular to the first orientation, wherein TSV cells having the first orientation and TSV cells having the second orientation are interspersed to reduce a TSV-induced stress in an IC substrate.

摘要翻译： 本发明的实施例提供了具有减少的通过硅通孔（TSV）的应力和相关IC设计结构和方法的集成电路（IC）。 在一个实施例中，本发明包括设计具有降低的衬底应力的集成电路（IC）的方法，所述方法包括：在IC设计文件中放置多个通过硅通孔（TSV）占位符单元，每个占位符单元具有未定义的 TSV方向 用具有第一取向的第一组TSV单元替换所述多个TSV占位符单元的第一部分; 以及用具有基本上垂直于第一取向的第二取向的第二组TSV单元替换多个TSV占位符单元的第二部分，其中具有第一取向的TSV单元和具有第二取向的TSV单元分散以减少TSV 在IC衬底中引起的应力。

公开(公告)号：US20120161299A1

公开(公告)日：2012-06-28

申请号：US13408141

申请日：2012-02-29

申请人： Jeffrey P. Gambino ,  Zhong-Xiang He ,  Kevin N. Ogg ,  Richard J. Rassel ,  Robert M. Rassel

发明人： Jeffrey P. Gambino ,  Zhong-Xiang He ,  Kevin N. Ogg ,  Richard J. Rassel ,  Robert M. Rassel

IPC分类号： H01L23/552 ,  G06F17/50

CPC分类号： H01L27/14623 ,  H01L27/14609 ,  H01L27/14632 ,  H01L27/14643

摘要： A CMOS image sensor pixel includes a conductive light shield, which is located between a first dielectric layer and a second dielectric layer. At least one via extends from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer is formed in the metal interconnect structure. The conductive light shield may be formed within a contact level between a top surface of a semiconductor substrate and a first metal line level, or may be formed in any metal interconnect via level between two metal line levels. The inventive CMOS image sensor pixel enables reduction of noise in the signal stored in the floating drain.

摘要翻译： CMOS图像传感器像素包括位于第一介电层和第二介电层之间的导电屏蔽。 在金属互连结构中形成有至少一个通孔从第二电介质层的顶表面延伸到第一介电层的底表面。 导电屏蔽可以形成在半导体衬底的顶表面和第一金属线电平之间的接触电平内，或者可以通过两个金属线电平之间的电平形成在任何金属互连中。 本发明的CMOS图像传感器像素能够减少存储在浮动漏极中的信号中的噪声。

公开(公告)号：US20120146158A1

公开(公告)日：2012-06-14

申请号：US12963054

申请日：2010-12-08

申请人： Alan B. Botula ,  Robert M. Rassel ,  Yun Shi ,  Mark Edward Stidham

发明人： Alan B. Botula ,  Robert M. Rassel ,  Yun Shi ,  Mark Edward Stidham

IPC分类号： H01L29/78 ,  G06F17/50 ,  H01L21/336

CPC分类号： H01L29/7833 ,  H01L21/26586 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate including a first source drain region, a second source drain region, and an intrinsic region therebetween; an asymmetric lightly doped drain (LDD) region within the substrate, wherein the asymmetric LDD region extends from the first source drain region into the intrinsic region between the first source drain region and the second source drain region; and a gate positioned atop the semiconductor substrate, wherein an outer edge of the gate overlaps the second source drain region. A related method and design structure are also disclosed.

摘要翻译： 公开了一种半导体器件。 半导体器件包括：半导体衬底，包括第一源极漏极区域，第二源极漏极区域及其之间的固有区域; 在所述衬底内的不对称轻掺杂漏极（LDD）区域，其中所述不对称LDD区域从所述第一源极漏极区域延伸到所述第一源极漏极区域和所述第二源极漏极区域之间的本征区域; 以及位于所述半导体衬底顶部的栅极，其中所述栅极的外边缘与所述第二源极漏极区重叠。 还公开了相关的方法和设计结构。

公开(公告)号：US08125013B2

公开(公告)日：2012-02-28

申请号：US12191385

申请日：2008-08-14

申请人： David S. Collins ,  Kai D. Feng ,  Zhong-Xiang Ile ,  Peter J. Lindgren ,  Robert M. Rassel

发明人： David S. Collins ,  Kai D. Feng ,  Zhong-Xiang Ile ,  Peter J. Lindgren ,  Robert M. Rassel

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L29/66181 ,  H01L29/945

摘要： A semiconductor structure and design structure includes at least a first trench and a second trench having different depths arranged in a substrate, a capacitor arranged in the first trench, and a via arranged in the second trench.

摘要翻译： 半导体结构和设计结构至少包括布置在衬底中的具有不同深度的第一沟槽和第二沟槽，布置在第一沟槽中的电容器和布置在第二沟槽中的通孔。

公开(公告)号：US20120013017A1

公开(公告)日：2012-01-19

申请号：US12835306

申请日：2010-07-13

申请人： Robert M. Rassel ,  Anthony K. Stamper ,  Daniel S. Vanslette

发明人： Robert M. Rassel ,  Anthony K. Stamper ,  Daniel S. Vanslette

IPC分类号： H01L23/48 ,  H01L21/50

CPC分类号： H01L25/16 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/552 ,  H01L23/645 ,  H01L24/13 ,  H01L24/16 ,  H01L2223/6661 ,  H01L2223/6672 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/157 ,  H01L2924/19011 ,  H01L2924/19042 ,  H01L2924/19103 ,  H01L2924/19107 ,  H01L2224/48091 ,  H01L2924/00014

摘要： Integrated structures having high performance CMOS active devices mounted on passive devices are provided. The structure includes an integrated passive device chip having a plurality of through wafer vias, mounted to a ground plane. The structure further includes at least one CMOS device mounted on the integrated passive device chip using flip chip technology and being grounded to the ground plane through the through wafer vias of the integrated passive device chip.

公开(公告)号：US08022496B2

公开(公告)日：2011-09-20

申请号：US11873696

申请日：2007-10-17

申请人： Douglas D. Coolbaugh ,  Alvin J. Joseph ,  Seong-dong Kim ,  Louis D. Lanzerotti ,  Xuefeng Liu ,  Robert M. Rassel

发明人： Douglas D. Coolbaugh ,  Alvin J. Joseph ,  Seong-dong Kim ,  Louis D. Lanzerotti ,  Xuefeng Liu ,  Robert M. Rassel

IPC分类号： H01L29/47

CPC分类号： H01L27/0814 ,  H01L27/0664 ,  H01L27/0823 ,  H01L29/0821 ,  H01L29/7371 ,  H01L29/868

摘要： A structure comprises a single wafer with a first subcollector formed in a first region having a first thickness and a second subcollector formed in a second region having a second thickness, different from the first thickness. A method is also contemplated which includes providing a substrate including a first layer and forming a first doped region in the first layer. The method further includes forming a second layer on the first layer and forming a second doped region in the second layer. The second doped region is formed at a different depth than the first doped region. The method also includes forming a first reachthrough in the first layer and forming a second reachthrough in second layer to link the first reachthrough to the surface.

摘要翻译： 一种结构包括具有形成在具有第一厚度的第一区域中的第一子集电极的单晶片和形成在具有不同于第一厚度的第二厚度的第二区域中的第二子集电极。 还可以设想一种方法，其包括提供包括第一层并在第一层中形成第一掺杂区的衬底。 该方法还包括在第一层上形成第二层并在第二层中形成第二掺杂区域。 第二掺杂区形成在与第一掺杂区不同的深度。 该方法还包括在第一层中形成第一通道并在第二层中形成第二通道以将第一通道连接到表面。