公开(公告)号：US12244670B2

公开(公告)日：2025-03-04

申请号：US18363005

申请日：2023-08-01

Applicant: Mellanox Technologies, Ltd.

Inventor： Liran Liss ,  Yamin Friedman ,  Michael Kagan ,  Diego Crupnicoff ,  Idan Burstein ,  Matty Kadosh ,  Tzah Oved ,  Dror Goldenberg ,  Ron Yuval Efraim ,  Alexander Eli Rosenbaum ,  Aviad Yehezkel ,  Rabia Loulou

IPC: H04L67/141 ,  G06F15/173 ,  H04L9/08 ,  H04L67/146 ,  H04L69/16

Abstract: Apparatus for data communication includes a network interface for connection to a packet data network and a host interface for connection to a host computer, which includes a central processing unit (CPU) and a host memory. Packet processing circuitry receives, via the host interface, from a kernel running on the CPU, associations between multiple remote direct memory access (RDMA) sessions and multiple different User Datagram Protocol (UDP) 5-tuple, which are assigned respectively to the RDMA sessions, and receives from an application running on the CPU a request to send an RDMA message, using a selected group of one or more of the RDMA sessions, to a peer application over the packet data network, and in response to the request, transmits, via the network interface, one or more data packets using a UDP 5-tuple that is assigned to one of the RDMA sessions in the selected group.

公开(公告)号：US12231495B2

公开(公告)日：2025-02-18

申请号：US18545057

申请日：2023-12-19

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Adi Merav Horowitz ,  Rabia Loulou ,  Omri Kahalon ,  Gal Shalom ,  Aviad Yehezkel ,  Asaf Schwartz ,  Liran Liss

IPC: G06F15/167 ,  H04L67/1097 ,  H04L67/146

Abstract: Systems and methods enable session sharing for session-based remote direct memory access (RDMA). Multiple queue pairs (QPs) can be added to a single session and/or session group where each of the QPs has a common remote. Systems and methods may query a session ID for an existing session group and then use the session ID with an add QP request to join additional QPs to an existing session. Newly added QPs may share one or more features with existing QPs of the session group, such as encryption parameters. Additionally, newly added QPs may be configured with different performance or quality of service requirements, thereby isolating performance, and permitting true scaling for high performance computing applications.

公开(公告)号：US20250028648A1

公开(公告)日：2025-01-23

申请号：US18353123

申请日：2023-07-17

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Daniel Marcovitch ,  Eliav Bar-Ilan ,  Liran Liss

IPC: G06F12/1072 ,  H04L67/1097

Abstract: A network adapter including a host interface, a network interface, packet processing circuitry, and Translation-as-a-Service (TaaS) circuitry. The host interface is to communicate with a host over a peripheral bus. The network interface is to send and receive packets to and from a network for the host. The packet processing circuitry is to process the packets. The TaaS circuitry is integrated in the network adapter and is to (i) receive from a requesting device a request to translate an input address into a requested address in a requested address space, (ii) translate the input address into the one or more requested addresses, and (iii) return the one or more requested addresses to the requesting device.

公开(公告)号：US12147716B2

公开(公告)日：2024-11-19

申请号：US17586417

申请日：2022-01-27

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Omri Kahalon ,  Gal Shalom ,  Aviad Yehezkel ,  Liran Liss ,  Oren Duer ,  Rabie Loulou ,  Maxim Gurtovoy

IPC: G06F3/00 ,  G06F3/06

Abstract: Methods and systems provided herein involve extracting an input/output (I/O) operation from a packet received over an I/O pipeline, the I/O operation comprising either a read request to read data from at least one storage device or a write request to write data to the at least one storage device; determining that an address associated with the I/O operation exists in a lookup table that is provided for thin provisioning of the at least one storage device; performing one or more RAID calculations associated with the at least one storage device based on the address and the I/O operation; and accessing the at least one storage device to perform the I/O operation based on the one or more RAID calculations; and second processing component configured to carry out a second set of operations that occur when the address associated with the I/O operation does not exist in the lookup table.

公开(公告)号：US12119958B2

公开(公告)日：2024-10-15

申请号：US18349148

申请日：2023-07-09

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Daniel Marcovitch ,  Idan Burstein ,  Liran Liss ,  Hillel Chapman ,  Dror Goldenberg ,  Michael Kagan ,  Aviad Yehezkel ,  Peter Paneah

IPC: H04L12/46 ,  G06F13/40 ,  G06F13/42 ,  G06F15/173

CPC classification number: H04L12/4625 ,  G06F13/4027 ,  G06F13/4208 ,  G06F15/17331 ,  H04L12/4633 ,  G06F2213/0026

Abstract: A cross-network bridging apparatus includes a bus interface and bridging circuitry. The bus interface is configured for connecting to a system bus. The bridging circuitry is configured to translate between (i) system-bus transactions that are exchanged between one or more local devices that are coupled to the system bus and served by the system bus and one or more remote processors located across a network from the apparatus, and (ii) data units that convey the system-bus transactions, for transmitting and receiving as network packets over the network to and from the remote processors.

公开(公告)号：US12117948B2

公开(公告)日：2024-10-15

申请号：US17976909

申请日：2022-10-31

Applicant: Mellanox Technologies, Ltd.

Inventor： Liran Liss ,  Rabia Loulou ,  Idan Burstein ,  Tzuriel Katoa

IPC: G06F13/28 ,  G06F13/42

CPC classification number: G06F13/28 ,  G06F13/4221

Abstract: Computing apparatus includes a central processing unit (CPU) and a root complex connected to the CPU and to a first peripheral component bus, which has at least a first downstream port for connection to at least one peripheral device. Switching logic has an upstream port for connection to a second downstream port on a second peripheral component bus of a host computer, and is connected to the root complex so that when a peripheral device is connected to the first downstream port on the first peripheral component bus, the switching logic presents the peripheral device to the host computer in an address space of the second peripheral component bus.

公开(公告)号：US20240338327A1

公开(公告)日：2024-10-10

申请号：US18747156

申请日：2024-06-18

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dimitrios Syrivelis ,  Paraskevas Bakopoulos ,  Ioannis (Giannis) Patronas ,  Elad Mentovich ,  James Stephen Fields ,  Haggai Eran ,  Liran Liss

IPC: G06F13/16

CPC classification number: G06F13/1642

Abstract: A system comprises a first processing block configured to receive, from a first local resource, a formatted transaction in a format that is not recognizable by a remote endpoint; determine a first transaction category, from among a plurality of transaction categories, of the formatted transaction based on content of the formatted transaction; perform one or operations on the formatted transaction based on the first transaction category to form a reformatted transaction in a format that is recognizable by the remote endpoint; and place the reformatted transaction in a queue for transmission to the remote endpoint.

公开(公告)号：US20240143528A1

公开(公告)日：2024-05-02

申请号：US17979013

申请日：2022-11-02

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Daniel Marcovitch ,  Eliav Bar-Ilan ,  Ran Avraham Koren ,  Liran Liss ,  Oren Duer ,  Shahaf Shuler

IPC: G06F13/28 ,  G06F13/42

CPC classification number: G06F13/28 ,  G06F13/4221 ,  G06F2213/0024

Abstract: A network adapter includes a network interface, a bus interface, a hardware-implemented data-path and a programmable Data-Plane Accelerator (DPA). The network interface is to communicate with a network. The bus interface is to communicate with an external device over a peripheral bus. The hardware-implemented data-path includes a plurality of packet-processing engines to process data units exchanged between the network and the external device. The DPA is to expose on the peripheral bus a User-Defined Peripheral-bus Device (UDPD), to run user-programmable logic that implements the UDPD, and to process transactions issued from the external device to the UDPD by reusing one or more of the packet-processing engines of the data-path.

公开(公告)号：US20240095205A1

公开(公告)日：2024-03-21

申请号：US17987904

申请日：2022-11-16

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Daniel Marcovitch ,  Liran Liss ,  Aviad Shaul Yehezkel ,  Rabia Loulou ,  Oren Duer ,  Shahaf Shuler ,  Chenghuan Jia ,  Philip Browning Johnson ,  Gal Shalom ,  Omri Kahalon ,  Adi Merav Horowitz ,  Arpit Jain ,  Eliav Bar-Ilan ,  Prateek Srivastava

IPC: G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4221 ,  G06F13/4022 ,  G06F13/404

Abstract: A system includes a bus interface and circuitry. The bus interface is configured to communicate with an external device over a peripheral bus. The circuitry is configured to support a plurality of widgets that perform primitive operations used in implementing peripheral-bus devices, to receive a user-defined configuration, which specifies a user-defined peripheral-bus device as a configuration of one or more of the widgets, and to implement the user-defined peripheral-bus device toward the external device over the peripheral bus, in accordance with the user-defined configuration.

公开(公告)号：US11929934B2

公开(公告)日：2024-03-12

申请号：US17730246

申请日：2022-04-27

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Liran Liss ,  Ortal Bashan ,  Aviad Levy ,  Lion Levi

IPC: H04L47/10

CPC classification number: H04L47/39

Abstract: A communication apparatus includes input circuitry, an encapsulator, transmission circuitry and flow control circuitry. The input circuitry is to receive packets from a data source in accordance with a first communication protocol that employs credit-based flow control. The encapsulator is to buffer the packets in a memory buffer and to encapsulate the buffered packets in accordance with a second communication protocol. The transmission circuitry is to transmit the encapsulated packets over a communication link in accordance with the second communication protocol. The flow control circuitry is to receive from the encapsulator buffer status indications that are indicative of a fill level of the memory buffer, and to exchange credit messages with the data source, in accordance with the credit-based flow control of the first communication protocol, responsively to the buffer status indications.