公开(公告)号：US20190206736A1

公开(公告)日：2019-07-04

申请号：US15857974

申请日：2017-12-29

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  Kurt D. Beigel

IPC: H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L23/522 ,  H01L23/528 ,  H01L27/092 ,  H01L27/115

CPC classification number: H01L21/8221 ,  H01L21/823871 ,  H01L21/823885 ,  H01L21/84 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/092 ,  H01L27/115 ,  H01L27/1207 ,  H01L29/7827 ,  H01L29/78642

Abstract: Some embodiments include an assembly having a CMOS tier. The CMOS tier includes a PMOS deck and an NMOS deck, with the decks being vertically offset relative to one another. The PMOS deck has p-channel transistors which are substantially identical to one another, and the NMOS deck has n-channel transistors which are substantially identical to one another. An insulative region is between the PMOS deck and the NMOS deck. The CMOS tier has one or more circuit components which include one or more of the n-channel transistors coupled with one or more of the p-channel transistors through one or more conductive interconnects extending through the insulative region. Some embodiments include methods of forming assemblies to comprise one or more CMOS tiers.

公开(公告)号：US20190074060A1

公开(公告)日：2019-03-07

申请号：US16176417

申请日：2018-10-31

Applicant: Micron Technology, Inc.

Inventor： Emiliano Faraoni ,  Scott E. Sills ,  Alessandro Calderoni ,  Adam Johnson

IPC: G11C13/00

Abstract: Memory systems and memory programming methods are described. According to one arrangement, a memory system includes a memory array comprising a plurality of memory cells individually configured to have a plurality of different memory states, access circuitry configured to apply signals to the memory cells to program the memory cells to the different memory states, and a controller to configured to control the access circuitry to apply a first of the signals to one of the memory cells to program the one memory cell from a first memory state to a second memory state different than the first memory state, to determine that the one memory cell failed to place into the second memory state as a result of the application of the first signal, and to control the access circuitry to apply a second signal to the one memory cell to program the one memory cell from the first memory state to the second memory state as a result of the determination, wherein the first and second signals have a different electrical characteristic.

公开(公告)号：US20190051823A1

公开(公告)日：2019-02-14

申请号：US16160518

申请日：2018-10-15

Applicant: Micron Technology, Inc.

Inventor： Timothy A. Quick ,  Eugene P. Marsh ,  Stefan Uhlenbrock ,  Chet E. Carter ,  Scott E. Sills

IPC: H01L45/00

Abstract: Memory cells are disclosed, which cells include a cell material and an ion-source material over the cell material. A discontinuous interfacial material is included between the cell material and the ion-source material. Also disclosed are fabrication methods and semiconductor devices including the disclosed memory cells.

公开(公告)号：US20180342294A1

公开(公告)日：2018-11-29

申请号：US16057170

申请日：2018-08-07

Applicant: Micron Technology, Inc.

Inventor： D.V. Nirmal Ramaswamy ,  Gurtej S. Sandhu ,  Lei Bi ,  Adam D. Johnson ,  Brent Keeth ,  Alessandro Calderoni ,  Scott E. Sills

IPC: G11C13/00 ,  G11C11/16

CPC classification number: G11C13/004 ,  G11C11/1673 ,  G11C13/0069 ,  G11C2013/0047 ,  G11C2013/0057

Abstract: The present disclosure includes apparatuses and methods for sensing a resistive memory cell. A number of embodiments include performing a sensing operation on a memory cell to determine a current value associated with the memory cell, applying a programming signal to the memory cell, and determining a data state of the memory cell based on the current value associated with the memory cell before applying the programming signal and a current value associated with the memory cell after applying the programming signal.

公开(公告)号：US20180331283A1

公开(公告)日：2018-11-15

申请号：US16041374

申请日：2018-07-20

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  Durai Vishak Nirmal Ramaswamy ,  Alessandro Calderoni

IPC: H01L45/00 ,  H01L27/11507 ,  H01L27/24

CPC classification number: H01L45/1233 ,  H01L27/11507 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/06

Abstract: An array of cross point memory cells comprises spaced first lines which cross spaced second lines. Two memory cells are individually between one of two immediately adjacent of the second lines and a same single one of the first lines.

公开(公告)号：US20180277602A1

公开(公告)日：2018-09-27

申请号：US15987613

申请日：2018-05-23

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  Durai Vishak Nirmal Ramaswamy

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2436 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/145 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1666 ,  H01L45/1691

Abstract: A method of forming an array of memory cells includes forming lines of covering material that are elevationally over and along lines of spaced sense line contacts. Longitudinal orientation of the lines of covering material is used in forming lines comprising programmable material and outer electrode material that are between and along the lines of covering material. The covering material is removed over the spaced sense line contacts and the spaced sense line contacts are exposed. Access lines are formed. Sense lines are formed that are electrically coupled to the spaced sense line contacts. The sense lines are angled relative to the lines of spaced sense line contacts and relative to the access lines. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US20180197864A1

公开(公告)日：2018-07-12

申请号：US15852870

申请日：2017-12-22

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills

IPC: H01L27/108

CPC classification number: H01L27/10802 ,  H01L27/10808 ,  H01L27/10852 ,  H01L28/91 ,  H01L29/7827

Abstract: A two transistor-one capacitor memory cell comprises first and second transistors laterally displaced relative one another. A capacitor is above the first and second transistors. The capacitor comprises a conductive first capacitor node directly above and electrically coupled to a first node of the first transistor. A conductive second capacitor node is directly above the first and second transistors and is electrically coupled to a first node of the second transistor. A capacitor insulator is between the first and second capacitor nodes. The second capacitor node comprises an elevationally-extending conductive pillar directly above the first node of the second transistor. The conductive pillar has an elevationally outer portion that is of four-sided diamond shape in horizontal cross-section. Other memory cells, including arrays of memory cells are disclosed as are methods.

公开(公告)号：US20180197862A1

公开(公告)日：2018-07-12

申请号：US15818571

申请日：2017-11-20

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  Durai Vishak Nirmal Ramaswamy

IPC: H01L27/108 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L49/02 ,  H01L21/311

CPC classification number: H01L27/1082 ,  H01L21/31111 ,  H01L21/31144 ,  H01L27/108 ,  H01L27/10858 ,  H01L27/10873 ,  H01L27/11507 ,  H01L27/11514 ,  H01L28/60 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/66666 ,  H01L29/7827

Abstract: A method of forming an array of capacitors and access transistors there-above comprises forming access transistor trenches partially into insulative material. The trenches individually comprise longitudinally-spaced masked portions and longitudinally-spaced openings in the trenches longitudinally between the masked portions. The trench openings have walls therein extending longitudinally in and along the individual trench openings against laterally-opposing sides of the trenches. At least some of the insulative material that is under the trench openings is removed through bases of the trench openings between the walls and the masked portions to form individual capacitor openings in the insulative material that is lower than the walls. Individual capacitors are formed in the individual capacitor openings. A line of access transistors is formed in the individual trenches. The line of access transistors electrically couples to the individual capacitors that are along that line. Other aspects, including structure independent of method, are disclosed.

公开(公告)号：US20180123035A1

公开(公告)日：2018-05-03

申请号：US15857448

申请日：2017-12-28

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Scott E. Sills ,  John K. Zahurak

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/085 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/148 ,  H01L45/16 ,  H01L45/1675

Abstract: Some embodiments include methods of forming memory cells. A series of rails is formed to include bottom electrode contact material. Sacrificial material is patterned into a series of lines that cross the series of rails. A pattern of the series of lines is transferred into the bottom electrode contact material. At least a portion of the sacrificial material is subsequently replaced with top electrode material. Some embodiments include memory arrays that contain a second series of electrically conductive lines crossing a first series of electrically conductive lines. Memory cells are at locations where the electrically conductive lines of the second series overlap the electrically conductive lines of the first series. First and second memory cell materials are within the memory cell locations. The first memory cell material is configured as planar sheets and the second memory cell material is configured as upwardly-opening containers.

公开(公告)号：US20170345972A1

公开(公告)日：2017-11-30

申请号：US15679958

申请日：2017-08-17

Applicant: Micron Technology, Inc.

Inventor： Scott D. Schellhammer ,  Scott E. Sills ,  Lifang Xu ,  Thomas Gehrke ,  Zaiyuan Ren ,  Anton J. De Villiers

IPC: H01L33/24 ,  H01L33/22 ,  H01L33/16 ,  H01L33/32 ,  H01L33/00

CPC classification number: H01L33/24 ,  H01L33/007 ,  H01L33/16 ,  H01L33/22 ,  H01L33/32

Abstract: Light emitting diodes and associated methods of manufacturing are disclosed herein. In one embodiment, a light emitting diode (LED) includes a substrate, a semiconductor material carried by the substrate, and an active region proximate to the semiconductor material. The semiconductor material has a first surface proximate to the substrate and a second surface opposite the first surface. The second surface of the semiconductor material is generally non-planar, and the active region generally conforms to the non-planar second surface of the semiconductor material.