公开(公告)号：US09368163B2

公开(公告)日：2016-06-14

申请号：US14482408

申请日：2014-09-10

Applicant: Micron Technology, Inc.

Inventor： Krishnam R. Datla ,  William H. Radke ,  Robin Sarno ,  Laszlo Borbely-Bartis ,  Ken Kannampuzha

IPC: G11C5/14

CPC classification number: G06F3/0625 ,  G06F3/0653 ,  G06F3/0688 ,  G11C5/14 ,  G11C16/30

Abstract: The present disclosure includes apparatuses and methods for power consumption control. A number of embodiments include determining power consumption information for each phase in a combination of phases of a command, and authorizing execution of at least one of the phases in the combination based, at least partially, on the power consumption information determined for the at least one of the phases.

Abstract translation: 本公开包括用于功耗控制的装置和方法。 多个实施例包括在命令的相位组合中确定每个阶段的功率消耗信息，并且至少部分地基于至少为至少确定的功耗信息授权执行组合中的至少一个相位的功率消耗信息 其中一个阶段。

公开(公告)号：US09361996B2

公开(公告)日：2016-06-07

申请号：US14474500

申请日：2014-09-02

Applicant: Micron Technology, Inc.

Inventor： Zhenlei Shen ,  William H. Radke

IPC: G11C16/04 ,  G11C16/34 ,  G11C11/56 ,  G11C16/10

CPC classification number: G11C16/34 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3404 ,  G11C16/3418

Abstract: Apparatuses and methods for inferring threshold voltage distributions associated with memory cells via interpolation are described herein. An example includes determining soft data for a group of memory cells each programmed to one of a number of data states, wherein the soft data comprises a number of different soft data values, determining a quantity of memory cells associated with each of the different soft data values, and inferring at least a portion of a threshold voltage distribution associated with the group of memory cells via an interpolation process using the determined quantities of memory cells associated with each of the different soft data values.

Abstract translation: 本文描述了用于通过插值推断与存储器单元相关联的阈值电压分布的装置和方法。 一个示例包括确定每个编程为多个数据状态之一的一组存储器单元的软数据，其中软数据包括多个不同的软数据值，确定与每个不同软数据相关联的存储器单元的数量 值，并且通过使用与每个不同软数据值相关联的确定量的存储器单元的内插处理来推断与该组存储器单元相关联的阈值电压分布的至少一部分。

公开(公告)号：US09342371B2

公开(公告)日：2016-05-17

申请号：US14278510

申请日：2014-05-15

Applicant: Micron Technology, Inc.

Inventor： Neal A. Galbo ,  Victor Y. Tsai ,  William H. Radke ,  Krishnam R. Datla

IPC: G06F9/00 ,  G06F9/24 ,  G06F13/00 ,  G06F9/50 ,  G06F9/44 ,  G06F12/02 ,  G06F3/06

CPC classification number: G06F9/5077 ,  G06F3/062 ,  G06F3/0644 ,  G06F3/0679 ,  G06F9/4401 ,  G06F12/0246 ,  G06F2212/7206

Abstract: The present disclosure includes boot partitions in memory devices and systems, and methods associated therewith. One or more embodiments include an array of memory cells, wherein the array includes a boot partition and a number of additional partitions. Sequential logical unit identifiers are associated with the additional partitions, and a logical unit identifier that is not in sequence with the sequential logical unit identifiers is associated with the boot partition.

公开(公告)号：US09230660B2

公开(公告)日：2016-01-05

申请号：US14224925

申请日：2014-03-25

Applicant: Micron Technology, Inc.

Inventor： Zhenlei Shen ,  William H. Radke

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C11/5621 ,  G11C16/0483 ,  G11C16/34

Abstract: Methods, devices, and systems for data modulation for groups of memory cells. Data modulation for groups of memory cells can include modulating N units of data to a combination of programmed states. Each memory cell of a group of G number of memory cells can be programmed to one of M number of programmed states, where M is greater than a minimum number of programmed states needed to store N/G units of data in one memory cell, and where the programmed state of each memory cell of the group is one of the combination of programmed states.

Abstract translation: 用于存储器单元组的数据调制的方法，设备和系统。 存储器单元组的数据调制可以包括将N个数据单元调制为编程状态的组合。 一组G个存储器单元的每个存储器单元可以被编程为M个编程状态中的一个，其中M大于在一个存储器单元中存储N / G个数据单元所需的编程状态的最小数量，以及 其中组的每个存储器单元的编程状态是编程状态的组合之一。

公开(公告)号：US20150348643A1

公开(公告)日：2015-12-03

申请号：US14826298

申请日：2015-08-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tommaso Vali ,  Giovanni Santin ,  Massimo Rossini ,  William H. Radke ,  Violante Moschiano

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/10

CPC classification number: G11C16/3436 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3422

Abstract: A memory device has an array of memory cells and a controller coupled to the array of memory cells. The controller is configured to determine a program window after a portion of a particular programing operation performed on the memory device is performed and before a subsequent portion of the particular programing operation performed on the memory device is performed. The controller is configured to determine the program window responsive to an amount of program disturb experienced by a particular state of a memory cell. The controller is configured to perform the subsequent portion of the particular programing operation performed on the memory device using the determined program window.

Abstract translation: 存储器件具有存储器单元的阵列和耦合到存储器单元阵列的控制器。 控制器被配置为在执行对存储器件执行的特定编程操作的一部分之后以及在执行对存储器件执行的特定编程操作的后续部分之后确定程序窗口。 控制器被配置为响应于由存储器单元的特定状态经历的程序干扰的量来确定程序窗口。 控制器被配置为使用所确定的程序窗口来执行在存储器设备上执行的特定编程操作的后续部分。

公开(公告)号：US20150333774A1

公开(公告)日：2015-11-19

申请号：US14811339

申请日：2015-07-28

Applicant: Micron Technology, Inc.

Inventor： Mustafa N. Kaynak ,  William H. Radke ,  Patrick R. Khayat ,  Sivagnanam Parthasarathy

IPC: H03M13/37 ,  G11C29/52 ,  G06F11/10 ,  H03M13/11 ,  H03M13/15

CPC classification number: H03M13/3753 ,  G06F11/10 ,  G06F11/1012 ,  G06F11/1068 ,  G11C29/52 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/1128 ,  H03M13/114 ,  H03M13/116 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/2906 ,  H03M13/3707

Abstract: The present disclosure includes apparatuses and methods related to stopping criteria for layered iterative error correction. A number of methods can include receiving a codeword with an error correction circuit, iteratively error correcting the codeword with the error correction circuit including parity checking the codeword on a layer-by-layer basis and updating the codeword after each layer. Methods can include stopping the iterative error correction in response to a parity check being correct for a particular layer.

Abstract translation: 本公开包括与停止用于分层迭代纠错的标准相关的装置和方法。 多种方法可以包括用纠错电路接收码字，用错误校正电路迭代地纠错码字，包括逐层地对码字进行奇偶校验，并在每层之后更新码字。 方法可以包括响应于针对特定层正确的奇偶校验来停止迭代纠错。

公开(公告)号：US20150255163A1

公开(公告)日：2015-09-10

申请号：US14719519

申请日：2015-05-22

Applicant: Micron Technology, Inc.

Inventor： William H. Radke ,  Zhenlei Shen ,  Peter Feeley

IPC: G11C16/26

CPC classification number: G11C16/26 ,  G11C7/14 ,  G11C11/26 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028 ,  G11C29/42 ,  G11C29/50004

Abstract: The present disclosure includes methods, devices, and systems for determining and using soft data in memory devices and systems. One or more embodiments include an array of memory cells and control circuitry coupled to the array. The control circuitry is configured to perform a number of sense operations on the memory cells using a number of sensing voltages to determine soft data associated with a target state of the memory cells, and adjust a sensing voltage used to determine the target state based, at least partially, on the determined soft data.

Abstract translation: 本公开包括用于在存储器设备和系统中确定和使用软数据的方法，设备和系统。 一个或多个实施例包括耦合到阵列的存储器单元阵列和控制电路。 控制电路被配置为使用多个感测电压对存储器单元执行多个感测操作，以确定与存储器单元的目标状态相关联的软数据，并且基于以下方式调整用于确定目标状态的感测电压： 最少部分地在确定的软数据上。

公开(公告)号：US09129684B2

公开(公告)日：2015-09-08

申请号：US14538020

申请日：2014-11-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tommaso Vali ,  Giovanni Santin ,  Massimo Rossini ,  William H. Radke ,  Violante Moschiano

IPC: G11C11/34 ,  G11C16/10 ,  G11C11/56 ,  G11C16/34 ,  G11C16/26

CPC classification number: G11C16/3436 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3422

Abstract: A memory device has an array of memory cells and a controller coupled to the array of memory cells. The controller is configured to determine a program window after a portion of a particular programming operation performed on the memory device is performed and before a subsequent portion of the particular programming operation performed on the memory device is performed. The controller is configured to determine the program window responsive to an amount of program disturb experienced by a particular state of a memory cell. The controller is configured to perform the subsequent portion of the particular programming operation performed on the memory device using the determined program window.

Abstract translation: 存储器件具有存储器单元的阵列和耦合到存储器单元阵列的控制器。 控制器被配置为在执行对存储器件执行的特定编程操作的一部分之后以及在执行对存储器件执行的特定编程操作的后续部分之后确定程序窗口。 控制器被配置为响应于由存储器单元的特定状态经历的程序干扰的量来确定程序窗口。 控制器被配置为使用所确定的程序窗口执行在存储器设备上执行的特定编程操作的后续部分。

公开(公告)号：US09075765B2

公开(公告)日：2015-07-07

申请号：US14029422

申请日：2013-09-17

Applicant: Micron Technology, Inc.

Inventor： William H. Radke ,  Victor Y. Tsai ,  James Cooke ,  Neal A. Galbo ,  Peter Feeley

IPC: G06F3/06 ,  G06F13/16 ,  G11C7/10 ,  G06F13/38 ,  G11C7/22

CPC classification number: G06F13/102 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/067 ,  G06F13/1684 ,  G06F13/4282 ,  G11C7/1045 ,  G11C7/22 ,  G11C7/222 ,  Y02D10/14 ,  Y02D10/151

Abstract: The present disclosure includes methods, devices, and systems for state change in systems having devices coupled in a chained configuration. A number of embodiments include a host and a number of devices coupled to the host in a chained configuration. The chained configuration includes at least one device that is not directly coupled to the host. The at least one device that is not directly coupled to the host is configured to change from a first communication state to a second communication state responsive to receipt of a command from the host.

Abstract translation: 本公开包括用于在具有以链式配置耦合的设备的系统中的状态改变的方法，设备和系统。 许多实施例包括以链式配置耦合到主机的主机和多个设备。 链接配置包括至少一个不直接耦合到主机的设备。 不直接耦合到主机的至少一个设备被配置为响应于从主机接收到命令而从第一通信状态改变到第二通信状态。

公开(公告)号：US20150023110A1

公开(公告)日：2015-01-22

申请号：US14474500

申请日：2014-09-02

Applicant: Micron Technology, Inc.

Inventor： Zhenlei Shen ,  William H. Radke

IPC: G11C16/34 ,  G11C16/10

CPC classification number: G11C16/34 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3404 ,  G11C16/3418

Abstract: The present disclosure includes apparatuses and methods for inferring threshold voltage distributions associated with memory cells via interpolation. A number of embodiments include determining soft data for a group of memory cells each programmed to one of a number of data states, wherein the soft data comprises a number of different soft data values, determining a quantity of memory cells associated with each of the different soft data values, and inferring at least a portion of a threshold voltage distribution associated with the group of memory cells via an interpolation process using the determined quantities of memory cells associated with each of the different soft data values.

Abstract translation: 本公开包括用于通过内插推断与存储器单元相关联的阈值电压分布的装置和方法。 多个实施例包括确定每个编程为多个数据状态中的一个的一组存储器单元的软数据，其中软数据包括多个不同的软数据值，确定与每个不同的数据状态相关联的存储器单元的数量 软数据值，并且通过使用与所述不同软数据值中的每一个相关联的确定量的存储器单元的内插处理来推断与所述存储器单元组相关联的阈值电压分布的至少一部分。