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公开(公告)号：US09536575B2
公开(公告)日：2017-01-03
申请号：US14877692
申请日：2015-10-07
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Wu-Chin Peng , Chun-Yi Lee , Ken-Hui Chen , Kuen-Long Chang , Chun Hsiung Hung
Abstract: An integrated circuit comprises a power supply input pin for receiving an off-chip supply voltage which can have a variable current, an on-chip power source to be powered by the off-chip supply voltage and which can provide a regulated current, a set of one or more circuits to be powered by at least one of the off-chip supply voltage and the on-chip power source, a configuration memory storing a set of one or more memory settings that indicate whether a circuit of said set of one or more circuits is powered by the on-chip power source, and control circuitry responsive to the at least one memory setting to control whether said circuit of said set of one or more circuits is powered by the on-chip power source.
Abstract translation: 集成电路包括用于接收可以具有可变电流的芯片外电源电压的电源输入引脚，由芯片外电源电压供电并且可以提供调节电流的片上电源，一组 一个或多个电路由芯片外电源电压和片上电源中的至少一个供电;配置存储器，存储一组或多个存储器设置，其指示所述一组或多个电路 更多的电路由片上电源供电，以及响应于至少一个存储器设置的控制电路，以控制所述一组或多个电路的所述电路是否由片上电源供电。
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公开(公告)号：US09535785B2
公开(公告)日：2017-01-03
申请号：US14158613
申请日：2014-01-17
Applicant: Macronix International Co., Ltd.
Inventor： Nai-Ping Kuo , Shih-Chang Huang , Chin-Hung Chang , Ken-Hui Chen , Kuen-Long Chang , Chun-Hsiung Hung
CPC classification number: G06F11/1048 , G06F2212/1036 , G11C16/3436
Abstract: A method of operating a memory storing data sets, and ECCs for the data sets is provided. The method includes when writing new data in a data set, computing and storing an ECC, if a number of addressable segments storing the new data and data previously programmed in the data set includes at least a predetermined number of addressable segments. The method includes storing indications for whether to enable or disable use of the ECCs, using the ECC and a first additional ECC bit derived from the ECC. The method includes reading from a data set an extended ECC including an ECC and a first additional ECC bit derived from the ECC, and enabling or disabling use of the ECC according to the indications stored for the data set. The method includes enabling use of ECCs for blank data sets, using the indications and a second additional ECC bit.
Abstract translation: 提供了一种操作存储数据集的存储器和数据集的ECC的方法。 如果存储新数据的多个可寻址段和先前在数据集中编程的数据包括至少预定数量的可寻址段，则该方法包括在将新数据写入数据集时，计算和存储ECC。 该方法包括使用ECC和从ECC导出的第一附加ECC比特来存储是否启用或禁止使用ECC的指示。 该方法包括从数据集读取包括ECC的扩展ECC和从ECC导出的第一附加ECC位，以及根据为数据集存储的指示启用或禁用ECC的使用。 该方法包括使用所述指示和第二附加ECC位使能ECC空白数据集。
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公开(公告)号：US09396769B1
公开(公告)日：2016-07-19
申请号：US14619810
申请日：2015-02-11
Applicant: Macronix International Co., Ltd.
Inventor： Kuen-Long Chang , Ken-Hui Chen , Ming-Chih Hsieh
IPC: G11C7/00
CPC classification number: G11C7/00 , G06F12/0246 , G11C7/1015 , G11C7/1045 , G11C16/06
Abstract: A memory device includes a memory array and a logic unit communicatively coupled to the memory array. The memory array includes a plurality of pages for storing array data and a plurality of extra arrays respectively corresponding to the plurality of pages for storing extra data. The logic unit is configured to receive a read instruction, and perform a read operation in a first access mode or in a second access mode. In the first access mode, the logic unit sequentially reads out the array data stored in the plurality of pages. In the second access mode, the logic unit sequentially reads out the array data stored in the plurality of pages and the extra data stored in the plurality of extra arrays.
Abstract translation: 存储器件包括存储器阵列和通信地耦合到存储器阵列的逻辑单元。 存储器阵列包括用于存储阵列数据的多个页面和分别对应于用于存储额外数据的多个页面的多个额外阵列。 逻辑单元被配置为接收读取指令，并且以第一访问模式或第二访问模式执行读取操作。 在第一访问模式中，逻辑单元顺序地读出存储在多个页面中的阵列数据。 在第二访问模式下，逻辑单元顺序地读出存储在多个页面中的阵列数据和存储在多个额外阵列中的额外数据。
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公开(公告)号：US20150370634A1
公开(公告)日：2015-12-24
申请号：US14841950
申请日：2015-09-01
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Shih-Chang Huang , Ken-Hui Chen , Chun-Hsiung Hung
CPC classification number: G06F11/1068 , G06F11/1052 , G11C29/52 , G11C2029/0411
Abstract: A method of operating a memory device storing ECCs for corresponding data is provided. The method includes writing an extended ECC during a first program operation, the extended ECC including an ECC and an extended bit derived from the ECC. The method includes overwriting the extended ECC with a pre-determined state during a second program operation to indicate the second program operation. The method includes, setting the ECC to an initial ECC state before the first program operation; during the first program operation, computing the ECC, changing the ECC to the initial ECC state if the computed ECC equals the pre-determined state; and changing the extended bit to an initial value if the ECC equals the initial ECC state. The method includes reading an extended ECC including an extended bit and an ECC for corresponding data, and determining whether to enable ECC logic using the extended ECC.
Abstract translation: 提供一种操作存储用于相应数据的ECC的存储设备的方法。 该方法包括在第一程序操作期间写入扩展ECC，扩展ECC包括ECC和从ECC导出的扩展位。 该方法包括在第二程序操作期间以预定状态重写扩展ECC以指示第二程序操作。 该方法包括：在第一程序操作之前将ECC设置为初始ECC状态; 在第一程序操作期间，如果所计算的ECC等于预定状态，则计算ECC，将ECC改变为初始ECC状态; 并且如果ECC等于初始ECC状态，则将扩展位改变为初始值。 该方法包括读取包括扩展位的扩展ECC和用于相应数据的ECC，并且确定是否使用扩展ECC来启用ECC逻辑。
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公开(公告)号：US20150323946A1
公开(公告)日：2015-11-12
申请号：US14274237
申请日：2014-05-09
Applicant: Macronix International Co., Ltd.
Inventor： Kuen-Long Chang , Ken-Hui Chen , Chin-Hung Chang , Chao-Hsin Lin
IPC: G05F1/46
Abstract: An integrated circuit device includes a pad adapted to receive a signal from an external driver. A state register is programmed with a state that indicates a voltage level to set for the pad during initialization of circuitry on the integrated circuit device responsive to the state for the pad. The voltage level may correspond to a logic low level or a logic high level. A voltage holding circuit is coupled to the pad and the state register, and is configured to force the pad to the voltage level in response to an event that causes the initialization.
Abstract translation: 集成电路器件包括适于从外部驱动器接收信号的焊盘。 状态寄存器被编程为响应于该焊盘的状态而指示在集成电路器件的电路初始化期间为焊盘设置的电压电平的状态。 电压电平可以对应于逻辑低电平或逻辑高电平。 电压保持电路耦合到焊盘和状态寄存器，并且被配置为响应于引起初始化的事件而迫使焊盘达到电压电平。
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Patent Agency Ranking
公开(公告)号：US09183937B2
公开(公告)日：2015-11-10
申请号：US13936620
申请日：2013-07-08
Applicant: Macronix International Co., Ltd.
Inventor： Ken-Hui Chen , Chun-Hsiung Hung , Kuen-Long Chang
CPC classification number: G11C16/16 , G11C16/345 , G11C16/3454
Abstract: Various aspects of a nonvolatile memory have an improved erase suspend procedure. A bias arrangement is applied to word lines of an erase sector undergoing an erase procedure interrupted by an erase suspend procedure. As a result, another operation performed during erase suspend, such as a read operation or program operation, has more accurate results due to decreased leakage current from any over-erased nonvolatile memory cells of the erase sector.
Abstract translation: 非易失性存储器的各个方面具有改进的擦除暂停过程。 偏移布置被施加到经历由擦除暂停过程中断的擦除过程的擦除扇区的字线。 结果，由于擦除扇区的任何被擦除的非易失性存储单元的漏电流减少，因此在诸如读操作或程序操作的擦除暂停期间执行的另一操作具有更精确的结果。
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公开(公告)号：US20150220390A1
公开(公告)日：2015-08-06
申请号：US14173873
申请日：2014-02-06
Applicant: Macronix International Co., Ltd.
Inventor： Chien-Hsin Liu , Su-Chueh Lo , Kuen-Long Chang , Ken-Hui Chen , Chun-Hsiung Hung
CPC classification number: G06F11/1072 , G06F11/1012 , H03M13/1575 , H03M13/19
Abstract: A programming method, a reading method and an operating system for a memory are provided. The programming method includes the following steps. A data is provided. A parity generation is performed to obtain an error-correcting code (ECC). The memory is programmed to record the data and the error-correcting code. The data is transformed before performing the parity generation, such that a hamming distance between two codes corresponding to two adjacent threshold voltage states in the data to be performed the parity generation is 1.
Abstract translation: 提供了一种用于存储器的编程方法，读取方法和操作系统。 编程方法包括以下步骤。 提供数据。 执行奇偶校验生成以获得纠错码（ECC）。 存储器被编程为记录数据和纠错码。 在执行奇偶校验生成之前变换数据，使得对应于待执行奇偶产生的数据中的两个相邻阈值电压状态的两个代码之间的汉明距离为1。
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公开(公告)号：US20150205666A1
公开(公告)日：2015-07-23
申请号：US14160612
申请日：2014-01-22
Applicant: Macronix International Co., Ltd.
Inventor： Chin-Hung Chang , Chia-Feng Cheng , Yu-Chen Wang , Ken-Hui Chen , Kuen-Long Chang
CPC classification number: G06F11/1044 , G06F11/1068 , G06F11/1076 , G06F2212/403 , G11C11/5635 , G11C16/00 , G11C16/14 , G11C16/16 , G11C16/3404 , G11C29/42
Abstract: An erasing method of a memory device is provided. The memory device includes a memory controller and a memory array having a first memory region and a second memory region. The first memory region and the second memory region share the same well. The erasing method comprising steps of: erasing the first memory region; and selectively programming the second memory region according to an error correction code algorithm.
Abstract translation: 提供了一种存储器件的擦除方法。 存储器件包括存储器控制器和具有第一存储器区域和第二存储器区域的存储器阵列。 第一存储器区域和第二存储器区域共享相同的阱。 擦除方法包括以下步骤：擦除第一存储区; 以及根据纠错码算法有选择地对第二存储区进行编程。
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公开(公告)号：US20150205665A1
公开(公告)日：2015-07-23
申请号：US14158613
申请日：2014-01-17
Applicant: Macronix International Co., Ltd.
Inventor： Nai-Ping Kuo , Shih-Chang Huang , Chin-Hung Chang , Ken-Hui Chen , Kuen-Long Chang , Chun-Hsiung Hung
IPC: G06F11/10
CPC classification number: G06F11/1048 , G06F2212/1036 , G11C16/3436
Abstract: A method of operating a memory storing data sets, and ECCs for the data sets is provided. The method includes when writing new data in a data set, computing and storing an ECC, if a number of addressable segments storing the new data and data previously programmed in the data set includes at least a predetermined number of addressable segments. The method includes storing indications for whether to enable or disable use of the ECCs, using the ECC and a first additional ECC bit derived from the ECC. The method includes reading from a data set an extended ECC including an ECC and a first additional ECC bit derived from the ECC, and enabling or disabling use of the ECC according to the indications stored for the data set. The method includes enabling use of ECCs for blank data sets, using the indications and a second additional ECC bit.
Abstract translation: 提供了一种操作存储数据集的存储器和数据集的ECC的方法。 如果存储新数据的多个可寻址段和先前在数据集中编程的数据包括至少预定数量的可寻址段，则该方法包括在将新数据写入数据集时，计算和存储ECC。 该方法包括使用ECC和从ECC导出的第一附加ECC比特来存储是否启用或禁止使用ECC的指示。 该方法包括从数据集读取包括ECC的扩展ECC和从ECC导出的第一附加ECC位，以及根据为数据集存储的指示启用或禁用ECC的使用。 该方法包括使用所述指示和第二附加ECC位使能ECC空白数据集。
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公开(公告)号：US20140376311A1
公开(公告)日：2014-12-25
申请号：US14451166
申请日：2014-08-04
Applicant: Macronix International Co., Ltd.
Inventor： Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen , Nai-Ping Kuo , Chin-Hung Chang , Chang-Ting Chen
CPC classification number: G11C16/16 , G11C16/0483 , G11C16/14 , G11C29/34 , G11C2029/2602
Abstract: A nonvolatile memory array has a multiple erase procedures of different durations. A block of memory cells of the array can be erased by one of the different erase procedures.
Abstract translation: 非易失性存储器阵列具有不同持续时间的多个擦除过程。 可以通过不同的擦除过程之一来擦除阵列的存储器单元的块。
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