公开(公告)号：US20200019347A1

公开(公告)日：2020-01-16

申请号：US16557245

申请日：2019-08-30

Applicant: Micron Technology, Inc.

Inventor： Daniele Balluchi ,  Paolo Amato

IPC: G06F3/06 ,  G06F11/07

Abstract: An apparatus can have an array of memory cells and a controller coupled to the array. The controller can be configured to read a group sentinel cells of the array and without reading a number of other groups of cells of the array to determine that data stored in the number of other groups of cells lacks integrity based on a determination that data stored in the group of sentinel cells lacks integrity.

公开(公告)号：US10534731B2

公开(公告)日：2020-01-14

申请号：US15924917

申请日：2018-03-19

Applicant: Micron Technology, Inc.

Inventor： Dionisio Minopoli ,  Gianfranco Ferrante ,  Antonino Caprí ,  Emanuele Confalonieri ,  Daniele Balluchi

IPC: G06F13/16 ,  G06F3/06 ,  G11C11/4096 ,  G11C11/4076 ,  G11C11/4093 ,  G06F13/42 ,  G06F13/32 ,  G06F13/22 ,  G06F9/38

Abstract: The present disclosure includes an interface for memory having a cache and multiple independent arrays. An embodiment includes a memory device having a cache and a plurality independent memory arrays, a controller, and an interface configured to communicate a plurality of commands from the controller to the memory device, wherein the interface includes a pin configured to activate upon a first one of the plurality of commands being received by the memory device and deactivate once all of the plurality of commands have been executed by the memory device.

公开(公告)号：US20190294363A1

公开(公告)日：2019-09-26

申请号：US15927383

申请日：2018-03-21

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Emanuele Confalonieri ,  Marco Dallabora ,  Roberto Izzi ,  Paolo Amato ,  Daniele Balluchi ,  Luca Porzio

IPC: G06F3/06 ,  G06F12/10

Abstract: An example apparatus comprises a hybrid memory system to couple to a host and a controller coupled to the hybrid memory system. The controller may be configured to cause data associated with a virtual memory location of the host to be selectively transferred to the hybrid memory system responsive to a determination that a main memory of the host experiences threshold amount of resource utilization.

公开(公告)号：US10083751B1

公开(公告)日：2018-09-25

申请号：US15664014

申请日：2017-07-31

Applicant: Micron Technology, Inc.

Inventor： Marco Dallabora ,  Paolo Amato ,  Daniele Balluchi ,  Danilo Caraccio ,  Emanuele Confalonieri

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0069 ,  G06F13/1668 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/0035 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0097 ,  G11C2013/0088

Abstract: The present disclosure includes apparatuses, and methods for data state synchronization. An example apparatus includes performing a write operation to store a data pattern in a group of resistance variable memory cells corresponding to a selected managed unit having a first status, updating a status of the selected managed unit from the first status to a second status responsive to performing the write operation, and providing data state synchronization for a subsequent write operation performed on the group by placing all of the variable resistance memory cells of the group in a same state prior to performing the subsequent write operation to store another data pattern in the group of resistance variable memory cells.

公开(公告)号：US10067890B2

公开(公告)日：2018-09-04

申请号：US15667358

申请日：2017-08-02

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Daniele Balluchi ,  Luca Porzio

IPC: G06F13/16 ,  G11C7/10

Abstract: Apparatuses and methods for variable latency memory operations are disclosed herein. An example apparatus may include a memory configured to provide first information during a variable latency period indicating the memory is not available to perform a command, wherein the first information is indicative of a remaining length of the variable latency period, the remaining length is one of a relatively short, normal, or long period of time, the memory configured to provide second information in response to receiving the command after the latency period.

公开(公告)号：US20170329534A1

公开(公告)日：2017-11-16

申请号：US15667358

申请日：2017-08-02

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Daniele Balluchi ,  Luca Porzio

IPC: G06F3/06

CPC classification number: G06F13/1689 ,  G06F13/161 ,  G11C7/106 ,  G11C7/1063 ,  G11C7/22 ,  G11C8/06 ,  G11C2207/2209 ,  G11C2207/2272 ,  G11C2207/229

Abstract: Apparatuses and methods for variable latency memory operations are disclosed herein. An example apparatus may include a memory configured to provide first information during a variable latency period indicating the memory is not available to perform a command, wherein the first information is indicative of a remaining length of the variable latency period, the remaining length is one of a relatively short, normal, or long period of time, the memory configured to provide second information in response to receiving the command after the latency period.

公开(公告)号：US09685234B2

公开(公告)日：2017-06-20

申请号：US15170609

申请日：2016-06-01

Applicant: Micron Technology, Inc.

Inventor： Daniele Balluchi ,  Corrado Villa

IPC: G11C11/34 ,  G11C16/10 ,  G11C13/00 ,  G11C16/26 ,  G11C8/08 ,  G11C16/32 ,  G11C16/08 ,  G11C16/34 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3436 ,  G11C16/3459 ,  G11C2213/79

Abstract: The disclosed technology relates to a memory device configured to perform multiple access operations in response to a single command received through a memory controller and a method of performing the multiple access operations. In one aspect, the memory device includes a memory array comprising a plurality of memory cells and a memory controller. The memory controller is configured to receive a single command which specifies a plurality of memory access operations to be performed on the memory array. The memory controller is further configured to cause the specified plurality of memory access operations to be performed on the memory array.

公开(公告)号：US09384830B2

公开(公告)日：2016-07-05

申请号：US14270944

申请日：2014-05-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Daniele Balluchi ,  Corrado Villa

IPC: G11C16/04 ,  G11C13/00 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3436 ,  G11C16/3459 ,  G11C2213/79

Abstract: The disclosed technology relates to a memory device configured to perform multiple access operations in response to a single command received through a memory controller and a method of performing the multiple access operations. In one aspect, the memory device includes a memory array comprising a plurality of memory cells and a memory controller. The memory controller is configured to receive a single command which specifies a plurality of memory access operations to be performed on the memory array. The memory controller is further configured to cause the specified plurality of memory access operations to be performed on the memory array.

Abstract translation: 所公开的技术涉及被配置为响应于通过存储器控制器接收的单个命令和执行多址访问操作的方法来执行多次访问操作的存储器件。 在一个方面，存储器件包括包括多个存储器单元和存储器控制器的存储器阵列。 存储器控制器被配置为接收指定要在存储器阵列上执行的多个存储器访问操作的单个命令。 存储器控制器还被配置为使得对存储器阵列执行指定的多个存储器访问操作。

公开(公告)号：US09224440B2

公开(公告)日：2015-12-29

申请号：US14472003

申请日：2014-08-28

Applicant: Micron Technology, Inc.

Inventor： Daniele Balluchi ,  Graziano Mirichigni

IPC: G06F12/00 ,  G11C7/10 ,  G06F12/06 ,  G11C16/10 ,  G11C16/32

CPC classification number: G06F3/0604 ,  G06F3/0629 ,  G06F3/0685 ,  G06F12/0638 ,  G06F2212/2022 ,  G11C7/1015 ,  G11C7/1078 ,  G11C7/1084 ,  G11C16/102 ,  G11C16/32 ,  Y02D10/13

Abstract: A non volatile memory device includes a first buffer register configured to receive and store the data to be stored into the memory device provided via a memory bus. A command window is activatable for interposing itself for access to a memory matrix between the first buffer element and the memory matrix. The command window includes a second buffer element that stores data stored in or to be stored into a group of memory elements. A first data transfer means executes a first transfer of the data stored in the second buffer register into the first buffer register during a first phase of a data write operation started by the reception of a first command. A second data transfer means receives the data provided by the memory bus and modifies, based on the received data, the data stored in the first buffer register during a second phase of the data write operation started by the reception of a second command. The first transfer means execute a second transfer of the modified data stored in the first buffer register into the second buffer register during a third phase of the data write operation. The second transfer is executed in response to the reception of a signal received by the memory bus together with the second command.

Abstract translation: 非易失性存储器件包括：第一缓冲寄存器，用于接收和存储要存储到经由存储器总线提供的存储器件中的数据。 命令窗口可激活以插入其自身以访问第一缓冲元件和存储器矩阵之间的存储器矩阵。 命令窗口包括第二缓冲器元件，其存储存储在存储器或存储到一组存储器元件中的数据。 在通过接收第一命令开始的数据写入操作的第一阶段期间，第一数据传送装置执行将存储在第二缓冲寄存器中的数据的第一传送到第一缓冲寄存器。 第二数据传送装置接收由存储器总线提供的数据，并且在通过接收第二命令开始的数据写入操作的第二阶段期间，基于接收的数据修改存储在第一缓冲寄存器中的数据。 第一传送装置在数据写入操作的第三阶段期间执行将存储在第一缓冲寄存器中的修改数据的第二传送到第二缓冲寄存器。 响应于与第二命令一起接收由存储器总线接收的信号执行第二传送。

公开(公告)号：US20150234601A1

公开(公告)日：2015-08-20

申请号：US14181089

申请日：2014-02-14

Applicant: Micron Technology, Inc.

Inventor： Victor Y. Tsai ,  Danilo Caraccio ,  Daniele Balluchi ,  Neal A. Galbo ,  Robert Warren

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0679 ,  G06F3/0688

Abstract: The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.

Abstract translation: 本公开包括用于命令排队的装置和方法。 许多实施例包括从主机在存储器系统处接收排队的命令请求，从存储器系统向主机发送指示存储器系统准备好在存储器系统的命令队列中接收命令的命令响应，以及 响应于发送命令响应，从所述主机接收在所述存储器系统处的所述命令的命令描述符块。