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    Memory Arrays and Methods Used in Forming a Memory Array Comprising Strings of Memory Cells
    91.
    发明申请
    Memory Arrays and Methods Used in Forming a Memory Array Comprising Strings of Memory Cells 有权

    公开(公告)号：US20250096042A1

    公开(公告)日：2025-03-20

    申请号：US18970741

    申请日：2024-12-05

    Applicant: Micron Technology, Inc.

    Inventor： Anilkumar Chandolu ,  Indra V. Chary

    IPC: H01L21/768 ,  H01L23/535 ,  H10B41/27 ,  H10B43/27

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. The memory-block regions comprise part of a memory-plane region. A pair of elevationally-extending walls are formed that are laterally-spaced relative one another and that are individually horizontally-longitudinally-elongated. The pair of walls are one of (a) or (b), where: (a): in the memory-plane region laterally-between immediately-laterally-adjacent of the memory-block regions; and (b): in a region that is edge-of-plane relative to the memory-plane region. Through the horizontally-elongated trenches and after forming the pair of walls, sacrificial material that is in the first tiers is isotropically etching away and replaced with conducting material of individual conducting lines. Other embodiments, including structure independent of method, are disclosed.

    Microelectronic devices with active source/drain contacts in trench in symmetrical dual-block structure, and related systems and methods
    93.
    发明授权
    Microelectronic devices with active source/drain contacts in trench in symmetrical dual-block structure, and related systems and methods 有权

    公开(公告)号：US12166094B2

    公开(公告)日：2024-12-10

    申请号：US17373258

    申请日：2021-07-12

    Applicant: Micron Technology, Inc.

    Inventor： Lifang Xu ,  Richard J. Hill ,  Indra V. Chary ,  Lars P. Heineck

    IPC: H01L29/417 ,  H01L21/768 ,  H01L23/528 ,  H01L29/40

    Abstract: Microelectronic devices include a tiered stack having vertically alternating insulative and conductive structures. A first series of stadiums is defined in the tiered stack within a first block of a dual-block structure. A second series of stadiums is defined in the tiered stack within a second block of the dual-block structure. The first and second series of stadiums are substantially symmetrically structured about a trench at a center of the dual-block structure. The trench extends a width of the first and second series of stadiums. The stadiums of the first and second series of stadiums have opposing staircase structures comprising steps at ends of the conductive structures of the tiered stack. Conductive source/drain contact structures are in the stack and extend substantially vertically from a source/drain region at a floor of the trench. Additional microelectronic devices are also disclosed, as are methods of fabrication and electronic systems.

    Integrated Assemblies, and Methods of Forming Integrated Assemblies
    96.
    发明公开
    Integrated Assemblies, and Methods of Forming Integrated Assemblies 审中-公开

    公开(公告)号：US20240015969A1

    公开(公告)日：2024-01-11

    申请号：US18371099

    申请日：2023-09-21

    Applicant: Micron Technology, Inc.

    Inventor： Anilkumar Chandolu ,  Indra V. Chary

    IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

    CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

    Abstract: Some embodiments include a method of forming an integrated assembly. Laterally alternating first and second sacrificial materials are formed over a conductive structure, and then a stack of vertically alternating first and second levels is formed over the sacrificial materials. The first levels include first material and the second levels include insulative second material. Channel-material-openings are formed to extend through the stack and through at least some of the strips. Channel-material-pillars are formed within the channel-material-openings. Slits are formed to extend through the stack and through the sacrificial materials. The first sacrificial material is replaced with first conductive material and then the second sacrificial material is replaced with second conductive material. At least some of the first material of the stack is replaced with third conductive material. Some embodiments include integrated assemblies.

    Integrated assemblies, and methods of forming integrated assemblies
    99.
    发明授权
    Integrated assemblies, and methods of forming integrated assemblies 有权

    公开(公告)号：US11800711B2

    公开(公告)日：2023-10-24

    申请号：US17322246

    申请日：2021-05-17

    Applicant: Micron Technology, Inc.

    Inventor： Anilkumar Chandolu ,  Indra V. Chary

    IPC: H01L27/11582 ,  H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

    CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

    Abstract: Some embodiments include a method of forming an integrated assembly. Laterally alternating first and second sacrificial materials are formed over a conductive structure, and then a stack of vertically alternating first and second levels is formed over the sacrificial materials. The first levels include first material and the second levels include insulative second material. Channel-material-openings are formed to extend through the stack and through at least some of the strips. Channel-material-pillars are formed within the channel-material-openings. Slits are formed to extend through the stack and through the sacrificial materials. The first sacrificial material is replaced with first conductive material and then the second sacrificial material is replaced with second conductive material. At least some of the first material of the stack is replaced with third conductive material. Some embodiments include integrated assemblies.

    Integrated Assemblies and Methods of Forming Integrated Assemblies
    100.
    发明公开
    Integrated Assemblies and Methods of Forming Integrated Assemblies 审中-公开

    公开(公告)号：US20230328975A1

    公开(公告)日：2023-10-12

    申请号：US18207499

    申请日：2023-06-08

    Applicant: Micron Technology, Inc.

    Inventor： Shuangqiang Luo ,  Lifang Xu ,  Indra V. Chary

    IPC: H10B41/40 ,  H10B43/27 ,  H10B41/27 ,  H10B41/10 ,  H10B43/10 ,  H10B43/40

    CPC classification number: H10B41/27 ,  H10B41/10 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

    Abstract: Some embodiments include an integrated assembly having a first memory region, a second memory region, and an intermediate region between the memory regions. A stack extends across the memory regions and the intermediate region. The stack includes alternating conductive levels and insulative levels. Channel-material-pillars are arranged within the memory regions. Memory-block-regions extend longitudinally across the memory regions and the intermediate region. Staircase regions are within the intermediate region. Each of the staircase regions laterally overlaps two of the memory-block-regions. First panel regions extend longitudinally across at least portions of the staircase regions. Second panel regions extend longitudinally and provide lateral separation between adjacent memory-block-regions. The second panel regions are of laterally different dimensions than the first panel regions and/or are compositionally different than the first panel regions. Some embodiments include methods of forming integrated assemblies.

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