公开(公告)号：US09552325B2

公开(公告)日：2017-01-24

申请号：US14302362

申请日：2014-06-11

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku ,  George Alan Wiley ,  Joseph Cheung

IPC: G06F13/42 ,  G06F13/364 ,  H04L7/033

CPC classification number: G06F13/4291 ,  G06F13/364 ,  G06F13/4282 ,  G06F13/4295 ,  H04L7/0331

Abstract: System, methods and apparatus are described that offer improved performance of a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control interface (CCI) operations. CCI extension (CCIe) devices are described. CCIe devices may be configured as a bus master or as a slave. In one method, a CCIe transmitter may generate a transition number from a set of bits, convert the transition number into a sequence of symbols, and transmit the sequence of symbols in the signaling state of a two-wire serial bus. Timing information may be encoded in the transitions between symbols of consecutive pairs of symbols in the sequence of symbols. For example, each transition may cause a change in the signaling state of at least one wire of the two-wire serial bus. A CCIe receiver may derive a receive clock from the transitions in order to receive and decode the sequence of symbols.

Abstract translation: 描述了提供用于内部集成电路（I2C）和/或相机控制接口（CCI）操作的串行总线的改进的性能的系统，方法和装置。 描述CCI扩展（CCIe）设备。 CCIe设备可以配置为总线主机或从机。 在一种方法中，CCIe发射机可以从一组比特生成转换号码，将转换号码转换为符号序列，并以两线串行总线的信令状态发送符号序列。 定时信息可以在符号序列中的连续符号对符号之间的转换中被编码。 例如，每个转换可能导致两线串行总线的至少一根线的信令状态改变。 CCIe接收机可以从转换中导出接收时钟，以便接收和解码符号序列。

公开(公告)号：US20160364353A1

公开(公告)日：2016-12-15

申请号：US15246098

申请日：2016-08-24

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku

IPC: G06F13/364 ,  G06F13/42 ,  G06F13/16

CPC classification number: G06F13/364 ,  G06F13/1673 ,  G06F13/24 ,  G06F13/362 ,  G06F13/378 ,  G06F13/4282

Abstract: A method for enabling 8-bit data word access over a protocol limited to 16-bit data word access is provided. Data may be encapsulated within the lowest 19 bits of a 20-bit number. If it is ascertained that an 8-bit data word is to be used in a system supporting only 16-bit data word access, a byte-enable indicator may be provided within a most significant bit of the 20-bit number while also allocating an 8-bit data region for transfer of the 8-bit data word. The 20-bit number may then be transcoded into a 12-digit ternary number, wherein a residual numerical region is defined as a number space by which a first numerical region defined for the 12-digit ternary number exceeds a second numerical region defined by the lowest 19 bits of the 20-bit number.

Abstract translation: 提供了一种通过限制为16位数据字访问的协议实现8位数据字访问的方法。 数据可以封装在20位数的最低19位中。 如果确定在仅支持16位数据字访问的系统中使用8位数据字，则可以在20位数的最高有效位内提供字节使能指示符，同时还分配 用于传输8位数据字的8位数据区。 20位数字然后可以被转码为12位三进制数，其中残差数字区被定义为数字空间，通过该数字空间，为12位三进制数定义的第一数值区域超过由第二数字区域定义的第二数值区域 最低19位的20位数。

公开(公告)号：US20160261400A1

公开(公告)日：2016-09-08

申请号：US15156555

申请日：2016-05-17

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku ,  Joseph Cheung ,  George Alan Wiley

IPC: H04L7/00 ,  H04L7/033

CPC classification number: H04L7/0087 ,  H03K3/017 ,  H03K5/13 ,  H03K5/133 ,  H03K5/134 ,  H03K5/14 ,  H03K5/153 ,  H03K5/1534 ,  H03K19/00 ,  H03K2005/00293 ,  H03L7/081 ,  H04L7/0037 ,  H04L7/033 ,  H04L7/0331

Abstract: A method, an apparatus, and a computer program product are described. The apparatus generates a receive clock signal for receiving data from a multi-wire open-drain link by determining a transition in a signal received from the multi-wire open-drain link, generating a clock pulse responsive to the transition, delaying the clock pulse by a preconfigured first interval if the transition is in a first direction, and delaying the clock by a preconfigured second interval if the transition is in a second direction. The preconfigured first and/or second intervals are configured based on a rise time and/or a fall time associated with the communication interface and may be calibrated by measuring respective delays associated with clock pulses generated for first and second calibration transitions.

Abstract translation: 描述了一种方法，装置和计算机程序产品。 该装置通过确定从多线开漏链路接收的信号中的转变来产生用于从多线开漏链路接收数据的接收时钟信号，响应于该转换产生时钟脉冲，延迟时钟脉冲 如果转换处于第一方向，则通过预先配置的第一间隔，并且如果转换处于第二方向，则将时钟延迟预先配置的第二间隔。 基于与通信接口相关联的上升时间和/或下降时间来配置预配置的第一和/或第二间隔，并且可以通过测量与为第一和第二校准转换产生的时钟脉冲相关联的相应延迟来校准预配置的第一和/或第二间隔。

公开(公告)号：US09374216B2

公开(公告)日：2016-06-21

申请号：US14220056

申请日：2014-03-19

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku ,  Joseph Cheung ,  George Alan Wiley

IPC: H04L7/033 ,  H03K5/1534 ,  H03K3/017 ,  H03K5/153 ,  H03L7/081 ,  H03K5/13 ,  H03K5/134 ,  H03K19/00 ,  H03K5/14 ,  H03K5/00 ,  H04L7/00

CPC classification number: H04L7/0087 ,  H03K3/017 ,  H03K5/13 ,  H03K5/133 ,  H03K5/134 ,  H03K5/14 ,  H03K5/153 ,  H03K5/1534 ,  H03K19/00 ,  H03K2005/00293 ,  H03L7/081 ,  H04L7/0037 ,  H04L7/033 ,  H04L7/0331

Abstract: A method, an apparatus, and a computer program product are described. The apparatus generates a receive clock signal for receiving data from a multi-wire open-drain link by determining a transition in a signal received from the multi-wire open-drain link, generating a clock pulse responsive to the transition, delaying the clock pulse by a preconfigured first interval if the transition is in a first direction, and delaying the clock by a preconfigured second interval if the transition is in a second direction. The preconfigured first and/or second intervals are configured based on a rise time and/or a fall time associated with the communication interface and may be calibrated by measuring respective delays associated with clock pulses generated for first and second calibration transitions.

Abstract translation: 描述了一种方法，装置和计算机程序产品。 该装置通过确定从多线开漏链路接收的信号中的转变来产生用于从多线开漏链路接收数据的接收时钟信号，响应于该转换产生时钟脉冲，延迟时钟脉冲 如果转换处于第一方向，则通过预先配置的第一间隔，并且如果转换处于第二方向，则将时钟延迟预先配置的第二间隔。 基于与通信接口相关联的上升时间和/或下降时间来配置预配置的第一和/或第二间隔，并且可以通过测量与为第一和第二校准转换产生的时钟脉冲相关联的相应延迟来校准预配置的第一和/或第二间隔。

公开(公告)号：US09363071B2

公开(公告)日：2016-06-07

申请号：US14199322

申请日：2014-03-06

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku ,  Chulkyu Lee ,  George Alan Wiley ,  Joseph Cheung

IPC: H04B3/00 ,  H04L7/033 ,  H04L7/027 ,  H04L7/00 ,  H04L25/49 ,  H04L25/493 ,  H03K5/1252 ,  H03K5/1534 ,  H04L25/14 ,  H04L25/02

CPC classification number: H04L7/033 ,  H03K5/1252 ,  H03K5/1534 ,  H04L7/0066 ,  H04L7/027 ,  H04L25/0272 ,  H04L25/14 ,  H04L25/49 ,  H04L25/4906 ,  H04L25/493

Abstract: A clock recovery circuit is provided comprising a receiver circuit and a clock extraction circuit. The receiver circuit may be adapted to decode a differentially encoded signal on a plurality of data lines, where at least one data symbol is differentially encoded in state transitions of the differentially encoded signal. The clock extraction circuit may be adapted to obtain a clock signal from state transition signals derived from the state transitions.

Abstract translation: 提供了一种包括接收机电路和时钟提取电路的时钟恢复电路。 接收器电路可以适于对多条数据线上的差分编码信号进行解码，其中至少一个数据符号在差分编码信号的状态转换中进行差分编码。 时钟提取电路可以适于从状态转换导出的状态转变信号获得时钟信号。

公开(公告)号：US20160149729A1

公开(公告)日：2016-05-26

申请号：US14949290

申请日：2015-11-23

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku

IPC: H04L25/03 ,  H04L27/38

CPC classification number: G06F11/1004 ,  H03M5/00 ,  H03M13/03 ,  H03M13/63 ,  H04L1/004 ,  H04L1/0041 ,  H04L1/0061 ,  H04L1/245 ,  H04L7/033 ,  H04L25/0264 ,  H04L25/0272 ,  H04L25/03286 ,  H04L25/14 ,  H04L25/493 ,  H04L27/38

Abstract: Apparatus, systems and methods for error detection in transmissions on a multi-wire interface are disclosed. A method for correcting transmission errors in multi-wire transition-encoded interface may include determining whether a symbol error is present in the sequence of symbols based on a value of an error detection code (EDC) in the received plurality of bits, generating one or more permutations of the sequence of symbols, where each permutation includes one symbol that is different from corresponding symbols in the sequence of symbols and different from corresponding symbols in other permutations. A permutation in the one or more permutations may be identified as including a corrected sequence of symbols when it produces a decoded EDC value that matches an expected EDC value. The expected EDC value may correspond to a predefined value for EDCs transmitted over the multi-wire interface to enable detection of up to two symbol errors at the receiver.

Abstract translation: 公开了用于在多线接口上的传输中的错误检测的装置，系统和方法。 用于校正多线转换编码接口中的传输错误的方法可以包括基于接收到的多个比特中的错误检测码（EDC）的值来确定符号序列中是否存在符号错误，生成一个或 符号序列的更多排列，其中每个置换包括不同于符号序列中的对应符号并且不同于其他排列中的对应符号的一个符号。 一个或多个排列中的排列可以被识别为当其产生与期望的EDC值匹配的解码的EDC值时包括经校正的符号序列。 期望的EDC值可以对应于通过多线接口发送的EDC的预定义值，以使得能够在接收器处检测多达两个符号错误。

公开(公告)号：US20160147596A1

公开(公告)日：2016-05-26

申请号：US14949435

申请日：2015-11-23

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku

IPC: G06F11/10 ,  H04L1/00

CPC classification number: G06F11/1004 ,  H03M5/00 ,  H03M13/03 ,  H03M13/63 ,  H04L1/004 ,  H04L1/0041 ,  H04L1/0061 ,  H04L1/245 ,  H04L7/033 ,  H04L25/0264 ,  H04L25/0272 ,  H04L25/03286 ,  H04L25/14 ,  H04L25/493 ,  H04L27/38

Abstract: Apparatus, systems and methods for error detection in transmissions on a multi-wire interface are disclosed. A method for transmitting data on the multi-wire interface includes transmitting data on a multi-wire interface includes obtaining a plurality of bits to be transmitted over a plurality of connectors, converting the plurality of bits into a sequence of symbols, and transmitting the sequence of symbols on the plurality of connectors. A predetermined number of least significant bits in the plurality of bits may be used for error detection. The predetermined number of least significant bits may have a constant value that is different from each of a plurality of error values. A symbol error affecting one or two symbols in the sequence of symbols may cause a decoded version of the predetermined number of least significant bits to have value that is one of a plurality of error values.

Abstract translation: 公开了用于在多线接口上的传输中的错误检测的装置，系统和方法。 一种用于在多线接口上发送数据的方法，包括：在多线接口上发送数据包括获得要在多个连接器上发送的多个比特，将所述多个比特转换成符号序列，以及发送所述序列 的多个连接器上的符号。 多个位中的预定数量的最低有效位可用于错误检测。 预定数量的最低有效位可以具有不同于多个误差值中的每一个的常数值。 影响符号序列中的一个或两个符号的符号错误可能导致预定数量的最低有效位的解码版本具有作为多个误差值之一的值。

公开(公告)号：US20160061780A1

公开(公告)日：2016-03-03

申请号：US14693681

申请日：2015-04-22

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku

IPC: G01N29/09 ,  H04N5/232 ,  G01N29/07

CPC classification number: H04N5/23264 ,  G02B27/646 ,  G03B13/36 ,  H04N5/23212 ,  H04N5/23248 ,  H04N5/23258 ,  H04N5/23287 ,  H04N2101/00 ,  H04N2201/0428 ,  H04N2201/046

Abstract: Methods and systems are disclosed for determining at least one actuation characteristic of an imaging device. For example, one method includes determining a target distance to move a lens by an actuator to focus a scene on an image sensor, where moving the lens by the actuator causes an associated lens vibration having at least one actuation characteristic, determining a scan sequence having a plurality of successive measurements, each measurement having at least a first measurement parameter and subsequent measurement parameter, each measurement parameter including at least one step and at least one time delay, moving the lens the target distance for each successive measurement based on the measurement parameters of each successive measurement, measuring a performance indicator of each successive measurement, and determining at least one actuation characteristic based on the first measurement parameter of the measurement having the highest performance indicator.

Abstract translation: 公开了用于确定成像装置的至少一个致动特性的方法和系统。 例如，一种方法包括确定由致动器移动透镜的目标距离以将场景聚焦在图像传感器上，其中由致动器移动透镜导致具有至少一个致动特性的相关联的透镜振动，确定具有 多个连续测量，每个测量具有至少第一测量参数和随后的测量参数，每个测量参数包括至少一个步骤和至少一个时间延迟，基于所述测量参数将所述透镜移动到每个连续测量的所述目标距离 测量每个连续测量的性能指标，以及基于具有最高性能指标的测量的第一测量参数来确定至少一个致动特性。

公开(公告)号：US20160028534A1

公开(公告)日：2016-01-28

申请号：US14875592

申请日：2015-10-05

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku

IPC: H04L7/00 ,  H04L25/02 ,  H04L7/033

CPC classification number: H04L7/0008 ,  H04L7/0087 ,  H04L7/0276 ,  H04L7/033 ,  H04L7/0331 ,  H04L25/0272 ,  H04L25/14

Abstract: System, methods and apparatus are described that facilitate communication of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A receiving device receives a sequence of symbols over a multi-wire link. The receiving device further receives a clock signal via a dedicated clock line, wherein the dedicated clock line is separate from, and in parallel with, the multi-wire link. The receiving device decodes the sequence of symbols using the clock signal. In an aspect, a second clock signal is embedded in guaranteed transitions between pairs of consecutive symbols in the sequence of symbols. Accordingly, the receiving device decodes the sequence of symbols using the clock signal received via the dedicated clock line while ignoring the second clock signal.

Abstract translation: 描述了促进通过多线数据通信链路，特别是在电子设备内的两个设备之间的数据通信的系统，方法和装置。 接收设备通过多线链路接收符号序列。 接收装置还经由专用时钟线接收时钟信号，其中专用时钟线与多线链路分离并与多线链路并联。 接收设备使用时钟信号来解码符号序列。 在一方面，第二时钟信号嵌入在符号序列中的连续符号对之间的保证转换中。 因此，接收装置使用经由专用时钟线接收的时钟信号来解码符号序列，同时忽略第二时钟信号。

公开(公告)号：US20150220472A1

公开(公告)日：2015-08-06

申请号：US14614188

申请日：2015-02-04

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku

IPC: G06F13/40 ,  G06F1/08

CPC classification number: G06F13/4068 ,  G06F1/08 ,  G06F13/4278

Abstract: Systems, methods and apparatus extract data and clocks from a multi-wire bus that includes a first lane operated in accordance with a camera control interface (CCIe) mode of operation or a first lane operated in accordance with an N! mode of operation. Timing information derived from a sequence of symbols received from the first lane may be used to deserialize data received on a second lane of the multi-wire bus or decode a sequence of symbols received on the second lane. The symbols in a pair of consecutive symbols transmitted on the first lane cause different signaling states. Data on the second lane may be deserialized using on the receive clock derived from the timing information. In a CCIe lane, the final symbol of the sequence of symbols may be suppressed or a setup condition curtailed when the final symbol produces a signaling state equivalent to the setup condition.

Abstract translation: 系统，方法和装置从多线总线提取数据和时钟，该多线总线包括根据照相机控制接口（CCIe）操作模式操作的第一通道或根据N＆ 操作模式。 从从第一通道接收的符号序列导出的定时信息可用于对在多线总线的第二通道上接收的数据进行反序列化或解码在第二通道上接收的符号序列。 在第一通道上发送的一对连续符号中的符号导致不同的信令状态。 可以使用从定时信息导出的接收时钟对第二通道上的数据进行反序列化。 在CCIe通道中，当最终符号产生与设置条件等效的信令状态时，符号序列的最终符号可被抑制或设置条件被限制。