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    SEMICONDUCTOR DEVICE AND DYNAMIC LOGIC CIRCUIT
    92.
    发明申请
    SEMICONDUCTOR DEVICE AND DYNAMIC LOGIC CIRCUIT 审中-公开

    公开(公告)号：US20200265887A1

    公开(公告)日：2020-08-20

    申请号：US16759013

    申请日：2018-11-12

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Tomoaki ATSUMI ,  Kiyoshi KATO ,  Shuhei MAEDA

    IPC: G11C11/4094 ,  H01L29/786 ,  H01L27/108

    Abstract: A semiconductor device whose operating speed is increased is provided. The semiconductor device includes a write word line, a read word line, a write bit line, a read bit line, a first wiring, and a memory cell. The memory cell includes three transistors of a single conductivity type and a capacitor. Gates of the three transistors are electrically connected to the write word line, a first terminal of the capacitor, and the read word line, respectively. A second terminal of the capacitor is electrically connected to the read bit line. A source and a drain of one transistor are electrically connected to the write bit line and the gate of another transistor, respectively. Two of the three transistors are electrically connected in series between the read bit line and the first wiring. A channel formation region of each of the three transistors includes, for example, a metal oxide layer.

    SEMICONDUCTOR DEVICE
    94.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20200176450A1

    公开(公告)日：2020-06-04

    申请号：US16779774

    申请日：2020-02-03

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO

    IPC: H01L27/105 ,  H01L29/786 ,  H01L29/24 ,  H01L27/12 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/11551

    Abstract: An object of one embodiment of the present invention is to provide a semiconductor device with a novel structure in which stored data can be stored even when power is not supplied in a data storing time and there is no limitation on the number of times of writing. The semiconductor device includes a first transistor which includes a first channel formation region using a semiconductor material other than an oxide semiconductor, a second transistor which includes a second channel formation region using an oxide semiconductor material, and a capacitor. One of a second source electrode and a second drain electrode of the second transistor is electrically connected to one electrode of the capacitor.

    SEMICONDUCTOR DISPLAY DEVICE
    96.
    发明申请
    SEMICONDUCTOR DISPLAY DEVICE 审中-公开

    公开(公告)号：US20170256570A1

    公开(公告)日：2017-09-07

    申请号：US15598651

    申请日：2017-05-18

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Shunpei YAMAZAKI ,  Satoshi MURAKAMI ,  Masahiko HAYAKAWA ,  Kiyoshi KATO ,  Mitsuaki OSAME

    IPC: H01L27/12 ,  G02F1/1362

    CPC classification number: H01L27/1248 ,  G02F1/136227 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/1255 ,  H01L27/13 ,  H01L27/3246 ,  H01L27/3276 ,  H01L33/52 ,  H01L51/5237 ,  H01L51/5253

    Abstract: It is an object of the present invention to provide a semiconductor display device having an interlayer insulating film which can obtain planarity of a surface while controlling film formation time, can control treatment time of heating treatment with an object of removing moisture, and can prevent moisture in the interlayer insulating film from being discharged to a film or an electrode adjacent to the interlayer insulating film. An inorganic insulating film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is formed so as to cover a TFT. Next, an organic resin film containing photosensitive acrylic resin is applied to the organic insulting film, and the organic resin film is partially exposed to light to be opened. Thereafter, an inorganic insulting film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is formed so as to cover the opened organic resin film. Then, in the opening part of the organic resin film, a gate insulating film and the two layer inorganic insulating film containing nitrogen are opened partially by etching to expose an active layer of the TFT.

    MEMORY DEVICE
    99.
    发明申请
    MEMORY DEVICE 有权
    内存设备

    公开(公告)号：US20160247548A1

    公开(公告)日：2016-08-25

    申请号：US15041435

    申请日：2016-02-11

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shunpei YAMAZAKI ,  Kiyoshi KATO ,  Takanori MATSUZAKI

    IPC: G11C5/10

    CPC classification number: G11C5/10 ,  G11C8/14 ,  G11C11/403 ,  G11C11/4085 ,  G11C11/4097 ,  G11C11/565 ,  G11C2207/101 ,  G11C2207/108 ,  H01L27/1156

    Abstract: To provide a memory device where multiple pieces of multilevel data can be written and read. The memory device includes first to fifth transistors, first to fourth capacitors, first to fourth nodes, and first and second wirings. The first node is connected to the first capacitor and a gate of the first transistor, the second node is connected to the second capacitor and a gate of the second transistor, the third node is connected to the third capacitor and a gate of the third transistor, and the fourth node is connected to the fourth capacitor and a gate of the fourth transistor. Multiple pieces of multilevel data is written to the first to fourth nodes through the second to fifth transistors. The second to fifth transistors each preferably include an oxide semiconductor in a channel formation region.

    Abstract translation: 提供可以写入和读取多个多级数据的存储器件。 存储器件包括第一至第五晶体管，第一至第四电容器，第一至第四节点以及第一和第二布线。 第一节点连接到第一电容器和第一晶体管的栅极，第二节点连接到第二电容器和第二晶体管的栅极，第三节点连接到第三电容器和第三晶体管的栅极 并且第四节点连接到第四电容器和第四晶体管的栅极。 多个多电平数据通过第二至第五晶体管写入第一至第四节点。 第二至第五晶体管各自优选地包括沟道形成区域中的氧化物半导体。

    SEMICONDUCTOR DEVICE, WIRELESS SENSOR, AND ELECTRONIC DEVICE
    100.
    发明申请
    SEMICONDUCTOR DEVICE, WIRELESS SENSOR, AND ELECTRONIC DEVICE 有权
    半导体器件，无线传感器和电子器件

    公开(公告)号：US20160094236A1

    公开(公告)日：2016-03-31

    申请号：US14862284

    申请日：2015-09-23

    Applicant: Semiconductor Energy Laboratory Co., LTD.

    Inventor： Yutaka SHIONOIRI ,  Kiyoshi KATO ,  Tomoaki ATSUMI

    IPC: H03M1/00 ,  H03M1/12 ,  H03M1/38

    CPC classification number: H03M1/002 ,  G11C27/02 ,  H03M1/1245 ,  H03M1/466

    Abstract: An object is to reduce power consumption of an analog-digital converter circuit. An analog potential obtained in a sensor or the like is held in a sample-and-hold circuit including a transistor with an extremely low off-state current. In the sample-and-hold circuit, the analog potential is held in a node which is able to hold a charge by turning off the transistor. Then, power supply to a buffer circuit or the like included in the sample-and-hold circuit is stopped to reduce power consumption. In a structure where a potential is held in each node, power consumption can be further reduced when a transistor with an extremely low off-state current is connected to a node holding a potential of a comparator, a successive approximation register, a digital-analog converter circuit, or the like, and power supply to these circuits is stopped.

    Abstract translation: 目的是减少模数转换器电路的功耗。 在传感器等中获得的模拟电位保持在包括极低截止电流的晶体管的采样保持电路中。 在采样保持电路中，模拟电位保持在能够通过关断晶体管来保持电荷的节点。 然后，停止对包含在取样保持电路中的缓冲电路等的电力供给，以降低功耗。 在每个节点中保持电位的结构中，当具有非常低的截止电流的晶体管连接到保持比较器的电位的节点，逐次逼近寄存器，数字模拟 转换器电路等，停止对这些电路的供电。

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